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| part number s5335 revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 s5335 pci bus controller, 3.3v data sheet s5335 pci bus controller (match maker)
s5335 ? pci bus controller, 3.3v ds1657 amcc confidential and proprietary revision 5.01 ? november 30, 2005 data sheet features ? pci 2.1 compliant master/slave device ? full 132 mbytes/sec transfer rate ? pci bus operation dc to 33 mhz ? 8/16/32 bit add-on user bus ? 3.3v power supply ? 5v tolerant i/os ? four definable pass-thru data channels ? two 32 byte internal fifos w/dma ? synchronous add-on bus operation ? mail box registers w/byte level status ? direct mail box data strobe/interrupts ? direct pci & add-on interrupt pins ? optional non-volatile memory boot loading ? optional expansion bios/post code ? 176 pin lqfp ? environmental friendly lead-free package option applications ? high speed networking ? digital video applications ? i/o communications ports ? high speed data input/output ? multimedia communications ? memory interfaces ? high speed data acquisition ? data encryption/decryption ? intel i960 interface ? general purpose pci interfacing description the pci local bus concept was developed to break the pc data i/o bottleneck and clearly opens the door to increasing system speed and expansion capabili- ties. the pci local bus moves high speed peripherals from the i/o bus and places them closer to the sys- tem?s processor bus, providing faster data transfers between the processor and peripherals. the pci local bus also addresses the industry?s need for a bus stan- dard which is not directly dependent on the speed, size and type of system processor. it represents the first microprocessor independent bus offering perfor- mance more than adequate for the most demanding applications such as full-motion video. applied micro circuits corporation (amcc), the pre- mier supplier of single ch ip solutions, has developed the s5335 to solve the problem of interfacing applica- tions to the pci lo cal bus while offering support for newer pci chipsets and operating systems. the s5335 is a powerful and flexible pci controller sup- porting several levels of inte rface sophistication. at the lowest level, it can serve simply as a pci bus target with modest transfer requirements. for high-perfor- mance applications, the s5335 can become a bus master to attain the pci local bus peak transfer capa- bility of 132 mbytes/sec. the s5335 was designed for 3.3v environment but its inputs/outputs are tolerant to 5v signaling. figure 1. s5335 block diagram pci local bus user application satellite receiv er/ modem proprietary backplane graphics/ mpeg/ grabber isdn fddi atm i/o audio serial/parallel nvram configuration space expansion bios amcc add-on local bus interface logic mux/demux buffers s5335 status registers configuration registers mailboxes fifos bus master transfer count & address registers pass-thru data & address registers pci local bus interface logic mux/demux buffers read/write control s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 3 data sheet table of contents features ...................................................................................................................... ........................................ 2 applications .................................................................................................................. .................................... 2 description ................................................................................................................... ..................................... 2 table of contents ............................................................................................................. ............................. 3 list of figures ............................................................................................................... ................................... 8 list of tables ................................................................................................................ .................................. 11 s5335 architecture ............................................................................................................ ........................... 13 s5335 register architec ture ................................................................................................... ......................... 13 pci configuration registers ............................ ....................................................................... ......................... 13 pci operation registers ....................................................................................................... ........................... 14 add-on bus operation registers ....................... ......................................................................... .................... 14 non-volatile memory in terface ................................................................................................. ....................... 14 mailbox operation ............................................................................................................. .............................. 15 pass-thru operation ................ ........................................................................................... ............................ 17 fifo pci bus mastering operation .............................................................................................. ................... 17 signal type definition ........................................................................................................ .............................. 19 non-volatile memory interface signals ......................................................................................... ... 23 add-on bus interface signals .................................................................................................. ................ 24 pci configuration registers ................................................................................................... ................. 27 vendor identification register (vid) .......................................................................................... ...................... 29 device identification register (did) .......................................................................................... ...................... 30 pci command register (pcicmd) ................................................................................................. ................ 31 pci status register (pcists) .................................................................................................. ....................... 33 revision identification register (rid) ........... ............................................................................. ...................... 35 class code register (clcd) .................................................................................................... ...................... 36 cache line size register (caln) ................... ............................................................................ .................... 40 latency timer register (lat) .. ................................................................................................ ....................... 41 header type register (hdr) .................................................................................................... ...................... 42 built-in self-test register (bist) ............................................................................................ ......................... 43 base address registers (badr) ................................................................................................. .................... 44 determining base address size ................................................................................................. ..................... 44 assigning the base address ..... ............................................................................................... ........................ 44 expansion rom base address register (xrom) .................................................................................... ...... 49 interrupt line register (intln ) ............................................................................................... ........................ 51 interrupt pin register (intpin) ............................................................................................... ........................ 52 minimum grant register (mingnt) ............................................................................................... ................. 53 maximum latency register (maxlat) ................. ............................................................................ .............. 54 outgoing mailbox registers (omb) .............................................................................................. ................... 56 incoming mailbox registers (imb) .............................................................................................. ..................... 56 fifo register port (fifo) ..................................................................................................... .......................... 56 pci controlled bus master write address register (mwar) ............ ........................................................... .. 57 pci controlled bus master write transfer count regist er (mwtc) ............................................................... 5 8 pci controlled bus master read address register (m rar) ........................................................................ .. 59 pci controlled bus master re ad transfer count register (mrtc) ............................................................... 60 mailbox empty full/status register (mbef) ..................................................................................... .............. 61 interrupt control/status register (intcsr) .... ................................................................................ ................ 63 master control/status register (mcsr) ......................................................................................... ................. 67 add-on bus operation registers ................................................................................................ ............ 70 s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 4 data sheet add-on incoming mailbox registers (aimbx) ..................................................................................... ............ 71 add-on outgoing mailbox register s (aombx) ..................................................................................... .......... 71 add-on fifo register port (afifo) ............................................................................................. .................. 71 add-on controlled bus master write address register (mwar) ................................................................... 7 2 add-on pass-thru address register (apta) ...................................................................................... ........... 73 add-on pass-thru da ta register (aptd) ......................................................................................... ............... 73 add-on controlled bus master read address register (mrar) ................................................................... 74 add-on empty/full status register (ambef) ..................................................................................... ............ 75 add-on interrupt control/status register (a int) ............................................................................... .............. 77 add-on general control/status register (agcsts) ............................................................................... ........ 80 add-on controlled bus master write transfer count register (mwtc) ..... ................................................... 83 add-on controlled bus master read transfer count register (mrtc) ......................................................... 84 initialization ................................................................................................................ .................................... 85 pci reset ........... ................ ................. ................ ................ ................ ............. ............ ....................................... 85 loading from byte-wide nv memories ............................................................................................ ....... 85 loading from serial nv memories ............................................................................................... ........... 86 pci bus configuration cycles .................................................................................................. ................ 88 expansion bios roms ... ................. ................ ................ ................ ............. ............. ............. ......................... 90 pci bus interface ............................................................................................................. .............................. 92 pci bus transactions .......................................................................................................... ......................... 92 pci burst transfers ........................................................................................................... .................................. 94 pci read transfers ............................................................................................................ ............................. 94 pci write transfers ........................................................................................................... .............................. 96 master-initiated termination .................................................................................................. .......................... 97 normal cycle completion ................................ ....................................................................... ......................... 97 initiator preemption .. ........................................................................................................ ............................... 98 master abort .................................................................................................................. .................................. 99 target-initiated termination .................................................................................................. .......................... 99 target disconnects ............................................................................................................ ............................ 100 target requested retries ...................................................................................................... ....................... 101 target aborts ................................................................................................................. ................................ 101 pci bus mastership ............................................................................................................ .......................... 103 bus mastership latency componen ts ............................................................................................. .............. 103 bus arbitration ............................................................................................................... ................................ 103 bus acquisition ............................................................................................................... ............................... 104 target latency ................................................................................................................ ............................... 104 target locking ................................................................................................................ ............................... 104 pci bus interrupts ............................................................................................................ .......................... 106 pci bus parity errors ......................................................................................................... ....................... 106 add-on bus interface .......................................................................................................... ....................... 107 add-on operation register accesses ............... ................ ................ ................ ................ ............. .... 107 add-on interface signals ...... ................................................................................................ ........................ 107 system signals ................................................................................................................ .............................. 107 register access signals ....................................................................................................... ......................... 107 asynchronous register accesses ................................................................................................ ................. 108 synchronous fifo and pass-thru da ta register accesses ........................................................................ 1 08 nv memory accesses through the add-on general contro l/status register ............................................... 108 s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 5 data sheet mailbox bus interface ......................................................................................................... ..................... 108 mailbox interrupts .. .......................................................................................................... .............................. 111 fifo bus interface ............................................................................................................ ........................... 111 fifo direct access inputs ..................................................................................................... ........................ 111 fifo status signals ........................................................................................................... ........................... 111 fifo control signals .......................................................................................................... ........................... 111 pass-thru bus interface ....................................................................................................... ................... 111 pass-thru status indicators ................................................................................................... ....................... 111 pass-thru control inputs ...................................................................................................... ......................... 111 non-volatile memory interface ................................................................................................. .......... 112 non-volatile memory interface signals ......................................................................................... ................ 112 accessing non-volatile memory ................................................................................................. ................... 112 nv memory device timing requir ements .......................................................................................... ............ 115 mailbox overview .............................................................................................................. .......................... 117 functional description ........................................................................................................ .................... 117 mailbox empty/full conditions ................................................................................................. ..................... 118 mailbox interrupts .. .......................................................................................................... .............................. 118 add-on outgoing mailbox 4, byte 3 access ......... ............................................................................. ........... 119 bus interface ................................................................................................................. ............................... 119 pci bus interface ............................................................................................................. ............................. 119 add-on bus interface .......................................................................................................... .......................... 119 8-bit and 16-bit add-on interfaces ............................................................................................ .................... 120 configuration ................................................................................................................. .............................. 120 mailbox status ................................................................................................................ ............................... 120 mailbox interrupts .. .......................................................................................................... .............................. 121 s5335 fifo overview ........................................................................................................... .......................... 124 functional description ........................................................................................................ .................... 124 fifo buffer management and endi an conversion .................................................................................. ..... 124 fifo advance conditions ....................................................................................................... ...................... 124 endian conversion ....................................... ...................................................................... ........................... 125 64-bit endian conversion ...................................................................................................... ........................ 126 add-on fifo status indicators ....................... .......................................................................... .................... 127 add-on fifo control signals .......................... ......................................................................... ..................... 127 pci bus mastering with the fifo ............................................................................................... ................... 127 add-on initiated bus ma stering ................................................................................................ ..................... 127 pci initiated bus mastering ................................................................................................... ........................ 128 address and transfer count regi sters .......................................................................................... ............... 128 bus mastering fifo management schemes ......................................................................................... ....... 128 fifo bus master cycle priority ................................................................................................ ..................... 129 fifo generated bus master interr upts .......................................................................................... ............... 129 bus interface ................................................................................................................. ............................... 129 fifo pci interface (target mode) .............................................................................................. ................... 129 fifo pci interface (initiator mode) ........................................................................................... .................... 130 fifo pci bus master reads ..................................................................................................... .................... 132 fifo pci bus master writes .................................................................................................... ..................... 132 add-on bus interface .......................................................................................................... .......................... 132 add-on fifo register accesses ................................................................................................. ................. 132 s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 6 data sheet add-on fifo direct access mode ................................................................................................ ................ 132 additional status/control signals for add-on initiated bus mastering .......................................................... 134 fifo generated add-on interrupts ................. ............................................................................. ................. 135 8-bit and 16-bit fifo ad d-on interfaces ....................................................................................... ............... 135 configuration ................................................................................................................. .............................. 136 fifo setup during initialization .................... .......................................................................... ....................... 136 fifo status and control bits .................................................................................................. ....................... 136 pci initiated fifo bus mastering setup ........................................................................................ ............... 137 pass-thru overview ............................................................................................................ ........................ 140 functional description ........................................................................................................ .................... 140 pass-thru transfers . .......................................................................................................... ........................... 140 pass-thru status/control signals ...................... ........................................................................ ................... 141 pass-thru add-on data bus sizi ng .............................................................................................. ................ 141 bus interface ................................................................................................................. ............................... 141 pci bus interface ............................................................................................................. ............................. 141 pci pass-thru single cycle accesse s ........................................................................................... ............... 141 pci pass-thru burst acce sses .................................................................................................. ................... 142 pci retry conditions .......................................................................................................... ........................... 142 pci write retries ............................................................................................................. .............................. 142 pci read retries .............................................................................................................. ............................. 143 add-on bus interface .......................................................................................................... .......................... 143 single cycle pass-thru writes ................................................................................................. ..................... 143 single cycle pass-thru reads ........................ .......................................................................... .................... 147 pass-thru burst writes ......... ............................................................................................... ......................... 147 pass-thru burst reads ............ ............................................................................................. ........................ 152 add-on pass-thru disconnect oper ation ......................................................................................... ............ 156 8-bit and 16-bit pass-thr u add-on bus interface ............................................................................... .......... 157 configuration ................................................................................................................. .............................. 161 s5335 base address register definition ........... ............................................................................. .............. 161 creating a pass-thru region .......................... ......................................................................... ..................... 161 accessing a pass-thru region .......................... ........................................................................ ................... 162 absolute maximum ratings ...................................................................................................... ................ 163 dc characteristics ............................................................................................................ ......................... 163 pci bus signals ............................................................................................................... .............................. 164 add-on bus signals ............................................................................................................ .............................. 165 ac characteristics ............................................................................................................ ......................... 166 pci bus timing ................................................................................................................ .............................. 166 add-on bus timings ............................................................................................................ ............................. 168 synchronous rdfifo# timing .................................................................................................... ................. 169 synchronous wrfifo# timing .................................................................................................... ................. 170 asynchronous rd# register access timing ......... .............................................................................. .......... 171 asynchronous wr# register access timing ....................................................................................... ......... 172 synchronous rd# fifo timing ................................................................................................... ................. 173 synchronous multiple rd# fifo timing .......................................................................................... ............. 174 synchronous wr# fifo timing ................................................................................................... ................. 175 synchronous multiple wr# fifo timing .......................................................................................... ............ 176 target s5335 pass-thru interface timing ....................................................................................... ............. 177 s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 7 data sheet target byte-wide nv memory interface timing .. ................................................................................. .......... 179 target timing ................................................................................................................. ............................... 181 document revision history ..................................................................................................... ................ 186 ordering informat ion .......................................................................................................... ............................ 188 s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 8 data sheet list of figures figure 1. s5335 block diagram ................................................................................................. .............................. 2 figure 2. s5335 pinout ........................................................................................................ .................................. 13 figure 3. pci and add-on local bus signal diagram ............................................................................. .............. 16 figure 4. pci pass-thru operatio n diagram ..................................................................................... .................... 17 figure 5. fifo pci bus mastering operation diagram ............................................................................ ............. 18 figure 6. s5335 signal pins ................................................................................................... ............................... 19 figure 7. vendor identification register ....... ............................................................................... ........................... 29 figure 8. device identification register ...................................................................................... ........................... 30 figure 9. pci command register ................................................................................................ .......................... 31 figure 10. pci status register .................... ............................................................................ .............................. 33 figure 11. revision identification register ..... .............................................................................. ......................... 35 figure 12. class code register ...................... .......................................................................... ............................. 36 figure 13. cache line size register .............. ............................................................................. .......................... 40 figure 14. latency timer regist er ............................................................................................. ............................ 41 figure 15. header type register ............................................................................................... ............................ 42 figure 16. built-in self test register ........................................................................................ ............................. 43 figure 17. base address register ? memory ..................................................................................... .................. 45 figure 18. base address register ? i/o ........................................................................................ ....................... 45 figure 19. expansion rom base ad dress register ................................................................................ .............. 49 figure 20. interrupt line regist er ............................................................................................ .............................. 51 figure 21. interrupt pi n register ............................................................................................. ............................... 52 figure 22. minimum grant regist er ............................................................................................. .......................... 53 figure 23. maximum latency register ........................................................................................... ....................... 54 figure 24. pci controlled bus master write address register ............. ...................................................... .......... 57 figure 25. pci controlled bus master write transfer count register ...... ...................................................... ....... 58 figure 26. pci controlled bus master read address register .................................................................... ......... 59 figure 27. pci controlled bus master read transfer count register ............................................................. ..... 60 figure 28. mailbox empty/full status register ... .............................................................................. ..................... 61 figure 29. interrup t control/status register .................................................................................. ........................ 63 figure 30. fifo management and endian control byte ............................................................................ ............ 64 figure 31. bus master control/st atus register ................................................................................. .................... 67 figure 32. add-on controlled bus ma ster write address register ................................................................ ....... 72 figure 33. add-on controlled bus ma ster read address register ................................................................. ...... 74 figure 34. add-on mailbox empty/fu ll status register .......................................................................... ............... 75 figure 35. add-on interrupt contro l/status register ........................................................................... .................. 77 figure 36. add-on general contro l/status register ............................................................................. ................ 80 figure 37. add-on controlled bus mast er write transfer coun t register ......................................................... ... 83 figure 38. add-on controlled bus mast er read transfer count register .......................................................... .. 84 figure 39. serial interfac e definition of start and stop ...................................................................... .................... 87 s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 9 data sheet figure 40. serial interface clock /data relationship ........................................................................... ................... 87 figure 41. serial interface byte access ? write ............................................................................... .................... 87 figure 42. serial interface byte access ? read ................................................................................ ................... 87 figure 43. pci ad bus definition during a type 0 c onfiguration access ......................................................... .... 88 figure 44. type 0 configuration read cycles ................................................................................... .................... 89 figure 45. type 0 configuration write cycles .................................................................................. ..................... 89 figure 46. zero wait state burst read pci bus transfer (s5335 as initiator) ................................................... ... 94 figure 47. single data phase pci bus read of s5335 re gisters (s5335 as target) ........................................... 95 figure 48. burst pci bus read attempt to s5335 register s (s5335 as target) ................................................... 9 5 figure 49. zero wait state burst write pci bus transfer (s5335 as initiator) .................................................. .... 96 figure 50. single data phase pci bus write of s5335 registers (s5335 as target) ........................................... 97 figure 51. master-initiated, normal comp letion (s5335 as either target or initiator) .......................................... .97 figure 52. master initiated termination due to preempti on and latency timer active (s5335 as master) .......... 98 figure 53. master initiated termination due to preempt ion and latency timer expired (s5335 as master) ........ 98 figure 54. master abort, no response .......................................................................................... ....................... 99 figure 55. target disconnect exampl e 1 (irdy# deasserted) ..................................................................... ....... 100 figure 56. target disconnect example 2 (irdy# asserted) ....................................................................... ......... 100 figure 57. target-initiated retry ............................................................................................. ............................. 101 figure 58. target abort exampl e ............................................................................................... .......................... 102 figure 59. pci bus arbitration and s5335 bus ownership example ................................................................ ... 102 figure 60. pci bus access latency components .................................................................................. ............. 103 figure 61. engaging the lock# signal .......................................................................................... ..................... 104 figure 62. access to a locked target by its owne r ............................................................................. ............... 105 figure 63. access attempt to a locked target .................................................................................. .................. 105 figure 64. error reporting signals ................. ........................................................................... .......................... 106 figure 65. asynchronous add-on op eration register read ........................................................................ ....... 109 figure 66. asynchronous add-on oper ation register write ....................................................................... ........ 109 figure 67. synchronous fifo or pa ss-thru data register read ................................................................... .... 110 figure 68. synchronous fifo or pa ss-thru data register write .................................................................. ...... 110 figure 69. nv memory read oper ation ........................................................................................... ..................... 115 figure 70. nv memory write operation ............... ........................................................................... ...................... 116 figure 71. block diagram - pci to add-on mailbox register ..................................................................... ......... 117 figure 72. block diagram - add-on to pci mailbox register .......... ........................................................... ......... 117 figure 73. intcsr fifo advance an d endian control bits ........................................................................ ........ 124 figure 74. 16-bit endian conversion .............. ............................................................................. ........................ 125 figure 75. 32-bit endian conversion .............. ............................................................................. ........................ 125 figure 76. 64-bit endian conversion .............. ............................................................................. ........................ 126 figure 77. pci read from a full s5335 fifo .................................................................................... .................. 130 figure 78. pci read from an empty s5335 fifo (target disconnect) .............................................................. . 130 figure 79. pci write to an empty s5335 fifo ... ................................................................................ ................. 131 figure 80. pci write to a full s533 5 fifo (target disconnect) ................................................................. ......... 131 s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 10 data sheet figure 81. synchronous fifo register burst read ac cess example ................................................................ . 133 figure 82. synchronous fifo register burst rdfifo# ac cess example .......................................................... 134 figure 83. single cycle pass-thru write ............ ........................................................................... ...................... 144 figure 84. single cycle pass-thru write with ptadr# ........................................................................... ........... 145 figure 85. single cycle pass-thru read with ptadr# ............................................................................ .......... 149 figure 86. pass-thru burst write .............................................................................................. .......................... 149 figure 87. pass-thru burst writes controlled by pt rdy# ........................................................................ ......... 150 figure 88. pass-thru burst read ............................................................................................... ......................... 152 figure 89. pci burst read controlled by ptrdy# ................................................................................ .............. 154 figure 90. target requested retry on the first pci data phase ................................................................. ....... 156 figure 91. target requested retry after the first data phase of a burs t operation .......................................... 157 figure 92. pass-thru signals after a target requested retry ................................................................... ......... 158 figure 93. pass-thru write to an 8-bit add-on de vice .......................................................................... .............. 160 figure 94. pci clock timing ................................................................................................... ............................. 166 figure 95. pci output timing .................................................................................................. ............................ 167 figure 96. pci input timing ................................................................................................... .............................. 167 figure 97. add-on clock timing ................................................................................................ .......................... 168 figure 98. pass-thru clock relation ship to pci clock .......................................................................... .............. 168 figure 99. synchronous rdfifo# timing ......................................................................................... .................. 169 figure 100. synchronous wrfifo# timing ........................................................................................ ................ 170 figure 101. asynchronous rd# fifo timing ........ .............................................................................. ................ 171 figure 102. asynchronous wr# fifo timing ....... ............................................................................... ............... 172 figure 103. synchronous rd# fifo timing ....................................................................................... ................. 173 figure 104. synchronous rd# fifo timing ....................................................................................... ................. 174 figure 105. synchronous wr# fifo timing ....................................................................................... ................ 175 figure 106. synchronous multiple wr# fifo timing .............................................................................. ............ 176 figure 107. pass-thru data register read timing ............................................................................... .............. 178 figure 108. pass-thru data regi ster write timing .............................................................................. ............... 178 figure 109. pass-thru status indicator timing ................................................................................. .................. 179 figure 110. nv memory read ti ming ............................................................................................. ...................... 180 figure 111. nv memory write timing ............................................................................................ ....................... 180 figure 112. irq# interrupt outp ut timing ...................................................................................... ..................... 181 figure 113. mailbox 4, byte 3 dir ect input timing ............................................................................. .................. 181 figure 114. s5335 pinout an d pin assignment - 176 lqfp (low profile quad flat package) ........................... 182 figure 115. package physical dimen sions - 176 lqfp ............................................................................ .......... 183 s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 11 data sheet list of tables table 1. pci configuration registers .......................................................................................... .......................... 13 table 2. pci operation registers .............................................................................................. ............................ 14 table 3. add-on bus operation re gisters ....................................................................................... ..................... 15 table 4. address and data pins ? pci local bus ................................................................................ ................ 20 table 5. system pins ? pci local bus .......................................................................................... ....................... 21 table 6. interface control pins ? pci bus signal .............................................................................. ................... 21 table 7. arbitration pins (bus masters only) ? pci local bus .................................................................. ........... 21 table 8. error reporting pins ? pci local bus ................................................................................. ................... 22 table 9. interrupt pin ? pci lo cal bus ........................................................................................ ......................... 22 table 10. serial nv devices ................................................................................................... ................................ 23 table 11. byte-wide nv devices ................................................................................................ ............................ 23 table 12. register access pins ................................................................................................ ............................. 24 table 13. fifo access pins .................................................................................................... .............................. 25 table 14. pass-thru interface pins ............................................................................................ ........................... 25 table 15. system pins ......................................................................................................... .................................. 26 table 16. configuration registers ............................................................................................. ............................ 27 table 17. vendor identification register ......... ............................................................................. .......................... 29 table 18. device identification register ......... ............................................................................. .......................... 30 table 19. pci command register ................................................................................................ ......................... 32 table 20. pci status register ................................................................................................. .............................. 34 table 21. revision identification register .................................................................................... .......................... 35 table 22. defined base class code s ............................................................................................ ........................ 36 table 23. base class code 00h: earl y, pre-2.0 specification devices ........................................................... ...... 37 table 24. base class code 01h: mass storage controllers ....................................................................... ........... 37 table 25. base class code 02h: network controllers ............................................................................ ............... 37 table 26. base class code 03h: display controllers ............................................................................ ................ 37 table 27. base class code 04h: multimedia device s ............................................................................. .............. 37 table 28. base class code 05h: memory controllers ............................................................................. .............. 37 table 29. base class code 06h: bridge devices ................................................................................. ................. 38 table 30. base class code 07h: simple communications controllers .............................................................. ... 38 table 31. base class code 08h: base system periph erals ........................................................................ .......... 38 table 32. base class code 09h: input devices .................................................................................. .................. 38 table 33. base class code 0ah: docking stations ............................................................................... ................ 39 table 34. base class code 0bh: processors ..................................................................................... ................... 39 table 35. base class code 0ch: serial bus contro llers ......................................................................... .............. 39 table 36. built-in self-test register ......................................................................................... ............................. 43 table 37. base address register ? memory (bit 0 = 0) .......................................................................... ............. 46 table 38. base address register ? i/o (bit 0 = 1) ............................................................................. .................. 46 table 39. read response (memory assigned) to an all-o nes write operation to a base address register ...... 47 s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 12 data sheet table 40. read response (i/o assigned) to an all-ones wr ite operation to a base address register ............... 48 table 41. expansion rom base address register ................................................................................. .............. 49 table 42. read response to expansion rom base address register (after a ll-ones written) ............................. 50 table 43. operation registers ? pci bus ............ ........................................................................... ..................... 55 table 44. mailbox empty/full status register .................................................................................. ..................... 62 table 45. interrupt control/status register ................................................................................... ........................ 65 table 46. bus master control/status register .................................................................................. ..................... 68 table 47. operation registers ? add-on interface .............................................................................. ................ 70 table 48. add-on mailbox empty/full status register ........................................................................... ............... 76 table 49. interrupt control/status register ................................................................................... ........................ 78 table 50. add-on general control/status register .............................................................................. ................. 81 table 51. valid external boot memory contents ... .............................................................................. .................. 86 table 52. pc compatible expansion rom ............ ............................................................................. ................... 90 table 53. pci data structure .................................................................................................. ............................... 91 table 54. supported pci bus commands .......................................................................................... ................... 93 table 55. target termination types ................... ......................................................................... ........................ 101 table 56. possible combinations of frame# and i rdy# ........................................................................... ....... 104 table 57. byte lane steering for pass-t hru data register read (pci write) .................................................... 1 59 table 58. byte lane steering for pass-t hru data register write (pci read) .................................................... 1 59 table 59. absolute maximum ratings ................... ......................................................................... ..................... 163 table 60. recommended operating condit ions and dc electrical characteristics ............................................ 163 table 61. pci bus signals ..................................................................................................... .............................. 164 table 62. add-on bus signals .................................................................................................. ........................... 165 table 63. pci bus timing ...................................................................................................... .............................. 166 table 64. synchronous rdfifo# timing .......................................................................................... .................. 169 table 65. synchronous wrfifo timing ........................................................................................... .................. 170 table 66. asynchronous rd# register access timing ............................................................................. .......... 171 table 67. asynchronous wr# register access timing ............................................................................. .......... 172 table 68. synchronous rd# fifo timing ......................................................................................... .................. 173 table 69. synchronous wr# fifo timing ......................................................................................... ................. 175 table 70. pass-thru interface timing ................. ......................................................................... ........................ 177 table 71. target byte-wide memory interface timing ............................................................................ ............ 179 table 72. target interrupt timing ............................................................................................. ........................... 181 table 73. mailbox timing ...................................................................................................... .............................. 181 table 74. s5335 numerical pin assignment - 176 lqfp ........................................................................... ......... 184 s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 13 data sheet the s5335 is an off-the-shelf, low-cost, standard prod- uct, which is pci 2.1 complia nt. and, since amcc is a member of the pci special interest group, the s5335 has been tested on various manufacturer?s pci moth- erboards, chip sets, pci bioss and operating systems. this removes the burden of compliance and compatibility testing from the designer and thus signifi- cantly reduces development time. utilizing the s5335 allows the designer to focu s on the actual application, not debugging the pci interface. the s5335 allows special direct data accessing between the pci bus and the user application through implementation of four definable pass-thru data chan- nels. each data channel is implemented by defining a host memory segment size and 8/16/32-bit user bus width. the addition of two 32 byte fifos, also used in s5335 bus mastering applicat ions, provides further versatility to data transfe r capabilities. fifo dma transfers are supported using address and transfer count registers. four 32-bit mailbox registers cou- pled with a status regist er and extensive interrupt capabilities provide flexib le user command or mes- sage transfers between the two buses. in addition, the s5335 also allows use of an external serial, or byte- wide non-volatile memory to perform any pre-boot ini- tialization requirements and to provide custom expansion bios or post code capability. s5335 architecture the block diagram in figure 2 above shows the major functional elements within the s5335. the s5335 pro- vides three physical bus inte rfaces: the pci local bus, the user local bus referred to as the add-on local bus and the optional serial and byte-wide non-volatile memory buses. data move ment between buses can take place through mailbox registers or the fifo data channel, or a user can define and enable one or more of the four pass-thru data channels. s5335 bus mas- ter or dma data transfers to and from the pci local bus are performed through the fifo data channel under either host or add-on software control or add- on hardware control using dedicated s5335 signal pins. the s5335 signal pins are shown in figure 3. the pci local bus signals are detailed on the left side; add-on local bus signal are detailed on the right side. all additional s5335 device control signals are shown on the lower right side. the s5335 supports a two wire serial nvram bus and a byte-wide eprom/flash bus. this allows the designer to customize the s5335 configuration by loading setup information on system power-up. figure 2. s5335 pinout s5335 register architecture control and configuration of the add-on local bus, and the s5335 itself, is performed through three pri- mary groups of registers. these groups consist of pci configuration registers, pci operation registers and add-on operation registers. these registers are user configurable through either their associated bus or from an external non-volatile memory device. this section will provide a brief overview of each of these register groups and the optional non-volatile interface. pci configuration registers all pci compliant devices are required to provide a group of configuration registers for the host system. these registers are polled during power up initializa- tion and contain specific device and add-in card product information including vendor id, device id, revision and the amount of memory required for prod- uct operation. the s5335 c an either load these registers with default values or initialize them from an external non-volatile memory area called ?configura- tion space?. the s5335 can accommodate a total of 256 bytes of external memory for this purpose. the first 64 bytes is reserved fo r user defined configuration data which is loaded into the pci configuration regis- ters during power-up initialization. the remaining 192 bytes may be used to implement an expansion bios or contain add-in card post code. table 1 shows all the s5335 pci configuration registers. add-on bus control s5933 register access pass-thru control/access serial bus config/bios opt. pci local bus s5935 control add-on data bus direct fifo access byte wide config/bios opt. bpclk rdfifo# sysrst# irq# wrfifo# dq[31:0] select# adr[6:2] be[3:0]# rd# wr# ptatn# ptburst# ptnum[1:0]# ptbe[3:0]# ptadr# ptwr ptrdy# rdempty wrfull ea[15:0] eq[7:0] ewr#/sda erd#/scl pclk inta# rst# ad[31:0] c/be[3:0]# frame# devsel# irdy# trdy# idsel# stop# lock# par perr# serr# s5335 gnt# req# mode snv s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 14 data sheet pci operation registers the second group of registers are the pci operation registers shown in table 2. this group consists of six- teen 32-bit (dword) register s accessible to the host processor from the pci local bus. these are the main registers through which the pci host configures s5335 operation and communicates with the add-on local bus. these registers encompass the pci bus incoming and outgoing mailboxes, fifo data channel, bus master address and count registers, pass-thru data channel registers and s5335 device status and control registers. add-on bus operation registers the third and last register group consists of the add- on operation registers, shown in table 3. this group of eighteen 32-bit (dword) registers is accessible to the add-on local bus. these are the main registers through which the add-on logic configures s5335 operation and communicates with the pci local bus. these registers encompass the add-on bus mail- boxes, add-on fifo, dma address/count registers (when add-on initiated bus mastering), pass-thru registers and status/control registers. non-volatile memory interface the s5335 contains a set of pci configuration regis- ters. these registers can be initialized with default values or with designer specified values contained in an external nvram. the nvram can be either a serial (2 kbytes, maximum) or a byte-wide device (64 kbytes, maximum). pci status pci command 04h class code revision id 08h built-in self test header type latency timer cache line size 0ch base address register 0 10h base address register 1 14h base address register 2 18h base address register 3 1ch base address register 4 20h reserved 24h reserved space 28h reserved space 2ch expansion rom base address 30h reserved space 34h reserved space 38h max. latency min. grant interrupt pin interrupt line 3ch table 1. pci configuration registers (continued) byte 3 byte 2 byte 1 byte 0 address table 2. pci operation registers pci operation registers address offset outgoing mailbox register 1 (omb1) 00h outgoing mailbox register 2 (omb2) 04h outgoing mailbox register 3 (omb3) 08h outgoing mailbox register 4 (omb4) 0ch incoming mailbox register 1 (imb1) 10h incoming mailbox register 2 (imb2) 14h incoming mailbox register 3 (imb3) 18h incoming mailbox register 4 (imb4) 1ch fifo register port (bidirectional) (fifo) 20h master write address register (mwar) 24h master write transfer count register (mwtc) 28h master read address register (mrar) 2ch master read transfer count register (mrtc) 30h mailbox empty/full status register (mbef) 34h interrupt control/status register (intcsr) 38h bus master control/status register (mcsr) 3ch s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 15 data sheet the optional nvram allows the add-on card manufac- turer to initialize the s5335 with his specific vendor id and device id numbers along with desired s5335 operation characteristics. the non-volatile memory feature also provides for the expansion bios and post code (power-on-self-test) options on the pci bus. mailbox operation the mailbox registers are divided into two four dword sets. each set is dedicated to one bus for transferring data to the other bus. figure 4 below shows a block diagram of the mailbox section of the s5335. the provision of mailbox registers provides an easy path for the transfer of user information (com- mand, status or parametric data) between the two buses. an empty/full indica tion for each mailbox reg- ister, at the byte level, is determined by polling a status register accessible to both the pci and add- on buses. providing mailbox byte level empty/full indi- cations allows for greater flexibility in 8-, 16- or 32-bit system interfaces. i.e., trans ferring a single byte to an 8-bit add-on bus without requiring the assembling or disassembling of 32-bit data. the generation of interrupts from mailbox registers is equivalent with the commonly known ?doorbell? interrupt technique. bit locations configured within the s5335?s operation registers select a mailbox and mailbox byte which is to generate an interrupt when full or touched. a mailbox in terrupt control register is then used to enable interrupt generation and to select if the interrupt is to be generated on the pci or add-on local bus. pci local bus interrupts may also be gen- erated from direct hardware interfacing due to a unique amcc feature. a dedi cated mailbox byte is directly accessible via a se t of hardware device signal pins. a mailbox load signal pin latches add-on bus data directly into the mailbox initiating a pci bus inter- rupt if enabled. mailbox data may also be read in a similar manner. this option is shared with the byte wide non-volatile memory signal pins. the s5335 must use the serial nvra m for the direct mailbox option signal pins to be available or they are assigned to the byte wide at power up. table 3. add-on bus operation registers add-on bus operation registers address incoming mailbox register 1 (aimb1) 00h incoming mailbox register 2 (aimb2) 04h incoming mailbox register 3 (aimb3) 08h incoming mailbox register 4 (aimb4) 0ch outgoing mailbox register 1 (aomb1) 10h outgoing mailbox register 2 (aomb2) 14h outgoing mailbox register 3 (aomb3) 18h outgoing mailbox register 4 (aomb4) 1ch fifo port (afifo) 20h bus master write address register (mwar) 24h pass-thru address register (apta) 28h pass-thru data register (aptd) 2ch bus master read address register (mrar) 30h mailbox empty/full status register (ambef) 34h interrupt control/status register (aint) 38h general control/status register (arcr) 3ch bus master write transfer count (mwtc) 58h bus master read transfer count (mrtc) 5ch s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 16 data sheet figure 3. pci and add-on local bus signal diagram p c i l o c a l b u s 32-bit master write address register s5335 a d d - o n l o c a l b u s b0 b0 b0 b1 b1 b1 b1 b2 b2 b2 b2 b3 b3 b3 b3 b0 b0 b0 b0 b1 b1 b1 b1 b2 b2 b2 b2 b3 b3 b3 b3 endian converter 32-bit master readaddress register 30-bit master read count register b0 b0 b0 b0 b1 b1 b1 b1 b2 b2 b2 b2 b3 b3 b3 b3 b0 b0 b0 b0 b1 b1 b1 b1 b2 b2 b2 b2 b3 b3 b3 b3 endian converter b0 28-bit master write count register s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 17 data sheet pass-thru operation pass-thru operation executes pci bus cycles in real time with the add-on bus. this allows the pci bus to directly read or write to add-on resources. the s5335 allows the designer to decla re up to four individual pass-thru regions. each region may be defined as 8, 16-, or 32-bits wide, mapped into host memory or i/o space and may be up to 512mb bytes in size. figure 5 right shows a block diagram of the s5335 pass-thru architecture. pass-thru operations are performed in pci target only mode, making this data channel useful for converting existing isa or eisa designs over to the fast pci architecture. the pass-thru data channel utilizes sep- arate add-on bus signal pins to reflect a pci bus read or write request. add-on logic decodes these signals to determine if it must read or write data to the s5335 to satisfy the request. information decoded includes pci request occurring, the byte lanes involved, the specific pass-thru region ac cessed and if the request is a burst or single-cycle access. all requested pass- thru address and data information is passed via add- on operation registers. pass-thru operation supports single pci data cycles and pci data bursts. during pci burst operations, the s5335 is capable of transferring data at the full pci bandwidth. should slower add-on logic be imple- mented, the s5335 automatically issues pci bus waits or a host retry indication until the requested transfer is satisfied. figure 4. pci pass-thru operation diagram fifo pci bus mastering operation fifo pci bus master data transfers are processed by one of two 8-dword fifos. the particular fifo selected for a data transfer is dependent only on the direction of data flow and is completely transparent to the user. internal s5335 decode logic selects the fifo that is dedicated to transferring data to the other bus. the way data is transferred by a fifo, is determined by operation and configur ation registers contained within the s5335. a fifo may be configured for either pci or add-on initiated bus mastering with program- mable byte advance conditions, read vs. write priorities and add-on bus widths. advance conditions allow the fifo to implement 8-, 16- or 32-bit bus widths. configuring the s5335 for bus master opera- tion enables separate address and data count registers, which are loaded with the pci memory address location and number of bytes to be read or written. this is accomplished by either the host cpu or add-on logic. data can be transferred between the two buses transparent to the pci host processor, how- ever, the add-on logic is required to service the s5335 add-on local bus. an indication of transfer completion can be seen by polling a status register done bit or s5335 signal pin or enabling a ?transfer count = 0? interrupt to either bus. further fifo configuration bits select 16, 32, or 64 bit endian conversion options for incoming and outgoing data. endian conversion allows an add-on processor and the host to transfer data in their native endian for- mat. other configuration bi ts determine if the add-on local bus width is 8, 16 or 32 bits. 16-bit bus configu- rations internally steer fifo data from the upper 16 bits of the dword and then to the lower 16-bits on alternate accesses. fifo pointers are then updated when appropriate bytes are accessed. other methods are available for 8-bit or 16-bit add-ons. efficient fifo management configuration schemes unique to the amcc s5335 specify how full or empty a fifo must be before it requests the pci local bus. these criteria include bus r equests when any of the 8 dwords are empty, or when four or more dwords are empty. this allows the designer to control how often the s5335 requests the bus. the s5335 always attempts to perform burst ope rations to empty or fill the fifos. further fifo capa bilities over the standard register access methods allow for direct hardware fifo access. this is provided through separate access pins on the s5335. other status output pins allow for easily cascading external fifos to the add- on design. pci local bus s5335 add-on pass-thru read data add-on pass-thru write data add-on local bus address latch add-on pass- thru address register s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 18 data sheet figure 5. fifo pci bus mastering operation diagram p c i l o c a l b u s 32-bit master write address register s5335 a d d - o n l o c a l b u s b0 b0 b0 b1 b1 b1 b1 b2 b2 b2 b2 b3 b3 b3 b3 b0 b0 b0 b0 b1 b1 b1 b1 b2 b2 b2 b2 b3 b3 b3 b3 endian converter 32-bit master readaddress register 30-bit master read count register b0 b0 b0 b0 b1 b1 b1 b1 b2 b2 b2 b2 b3 b3 b3 b3 b0 b0 b0 b0 b1 b1 b1 b1 b2 b2 b2 b2 b3 b3 b3 b3 endian converter b0 28-bit master write count register s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 19 data sheet signal type definition the following signal type definiti ons [in, out, t/s, s/t/s and o/d] are tak en from revision 2.1 of the pci local bus specification. note that a # symbol at the end of a signal name denotes that t he active state occurs when the signal is at a low voltage. when no # symbol is present, the signal is active high. figure 6. s5335 signal pins in input is a standard input-only signal. out totem pole output is a standard active driver. t/s tri-state ? is a bidirectiona l, tristate input/output pin. s/t/s sustained tri-state is an active low tristate signal owned and driven by one and only one agent at a time. the agent that drives an s/t/s pin low must drive it high for at least one clock before letting it float. a new agent cannot start driv- ing a s/t/s signal any sooner than one clo ck after the previous owner tri-states it. a pull-up is required to sustain the inactive state until another agent drives it, and must be provided by the central source. o/d open drain allows multiple devices to share as a wire-or. pc l k in ta# rst# ad[31:0] c/be[3:0]# req# gnt# fr ame# d evsel # ir d y# trdy# id sel stop# lock# par # perr# serr# mod e r svd sn v bpc l k ir q# sysr st dq[31:0] sel ec t# ad r [6 :2] be[3:0]# rd# wr# ptatn # ptbu r st# ptn u m[1 :0] ptbe[3 :0 ]# ptad r # ptw r ptr d y# rdfifo# wrfifo# r d empty wrfull ea[15:0] eq[7 :0 ] ewr#/sda erd#/scl add-on bus control s5335 register access pass-thru control/ access serial config/bios opt. direct fifo access byte wide config /bios opt. pci local bus s5335 control s5335 add-on data bus s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 20 data sheet table 4. address and data pins ? pci local bus signal type description ad[31:00] t/s local bus address/data lines. address and da ta are multiplexed on the same pins. each bus opera- tion consists of an address phase followed by one or more data phases. address phases are identified when the control signal, frame#, is asserted. data transfers occur during those clock cycles in which control signals irdy# and trdy# are both asserted. c/be[3:0]# t/s bus command and byte enables. these are mu ltiplexed on the same pins. during the address phase of a bus operation, these pins identify the bus comm and, as shown in the table below. during the data phase of a bus operation, these pins are used as byte enables, with c/be[0]# enabling byte 0 (least significant byte) and c/be[3]# enabli ng byte 3 (most significant byte). c/be[3:0]# description (during address phase) 0000interrupt acknowledge 0 0 0 1 special cycle 0010i/o read 0 0 1 1 i/o write 0100reserved 0101reserved 0 1 1 0 memory read 0 1 1 1 memory write 1000reserved 1001reserved 1 0 1 0 configuration read 1 0 1 1 configuration write 1 1 0 0 memory read - multiple 1 1 0 1 dual address cycle 1 1 1 0 memory read line 1 1 1 1 memory write and invalidate par t/s parity. this signal is even parity across the enti re ad[31:00] field along with the c/be[3:0]# field. the parity is stable in the clock following the addre ss phase and is sourced by the master. during the data phase for write operations, the bus master sources this signal on the clock following irdy# active; during the data phase for read operations, this signal is sourced by the target and is valid on the clock following trdy# active. the par signal therefore ha s the same timing as ad[31:00}, delayed by one clock. s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 21 data sheet table 5. system pins ? pci local bus signal type description clk in clock. the rising edge of this signal is the re ference upon which all other signals are based, with the exception of rst# and the interrup t (irqa#-). the maximum frequency for this signal is 33 mhz and the minimum is dc (0 hz). rst# in reset. this signal is used to bring all other signals within this device to a known, consistent state. all pci bus interface output signals are not driven (tri-stated), and open drain signals such as serr# are floated. table 6. interface control pins ? pci bus signal signal type description frame# s/t/s frame. this signal is driven by the current bus master and identifies both the beginning and duration of a bus operation. when frame# is first asserted, it indicates that a bus transaction is beginning and that valid addresses and a corresponding bus comma nd are present on the ad [31:00] and c/be[3:0] lines. frame# remains asserted during the data transfer portion of a bus operation and is deasserted to signify the final data phase. irdy# s/t/s initiator ready. this signal is sourced by the bus master and indicates that the bus master is able to complete the current data phase of a bus transaction. fo r write operations, it indi cates that valid data is on the ad[31:00] pins. wait states occur until both trdy# and irdy# are asserted together. trdy# s/t/s target ready. this signal is sourced by the selected target and indicates that the target is able to com- plete the current data phase of a bus transaction. for read operations, it indicate s that the target is pro- viding valid data on the ad[31:00] pins. wait stat es occur until both trdy # and irdy# are asserted together. stop# s/t/s stop. the stop signal is sourced by the selected target and conveys a request to the bus master to stop the current transaction. lock# in lock. the lock signal provides for the exclusive use of a resource. the s5335 may be locked as a tar- get by one master at a time. the s5335 cannot lock a target when it is a master. idsel in initialization device select. this pin is used as a chip select during configuration read or write opera- tions. devsel# s/t/s device select. this signal is sourced by an active target upon decoding th at its address and bus com- mands are valid. for bus masters, it indicates whether any device has decoded the current bus cycle. table 7. arbitration pins (bus masters only) ? pci local bus signal type description req# out request. this signal is sour ced by an agent wishing to become the bu s master. it is a point-to-point signal and each master has its own req#. gnt# in grant. the gnt# signal is a dedicated, point-to-poin t signal provided to each potential bus master and sig- nifies that access to the bus has been granted. s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 22 data sheet table 8. error reporting pins ? pci local bus signal type description perr# s/t/s parity error. this pin is used for reporting parity errors during the data portion of a bus transaction for all cycles except a special cycle. it is sourced by the agent receiving data and driven acti ve two clocks fol- lowing the detection of the error. this signal is driven in active (high) for one clock cycle prior to returning to the tri-state condition. serr# o/d system error. this pin is used for reporting addres s parity errors, data parity errors on special cycle com- mands, or any error condition having a catastrophic system impact. table 9. interrupt pin ? pci local bus signal type description inta# o/d interrupt a. this pin is a level sensitive, low acti ve interrupt to the host. the inta# interrupt must be used for any single function device requiring an interrupt capability. s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 23 data sheet non-volatile memory interface signals this signal grouping provides for connection to exter- nal non-volatile memories. either a serial or byte-wide device may be used. the serial interface shares the read and write control pins used for interfacing with byte-wide memory devices. since it is intended that only one (serial or byte wide) configuration be used in any given imple- mentation, separate descriptions are provided for each. the s5335 provides the pins necessary to inter- face to a byte wide non-volatile memory. when they are connected to a properly configured serial memory, these byte wide interface pins assume alternate func- tions. these alternate functions include added external fifo status flags, fifo reset control, add-on control for bus mastering and a hardware interface mailbox port.. table 10. serial nv devices signal type description scl out serial clock. this output is intended to drive a tw o-wire serial interface and functions as the bus?s master. it is intended that this signal be di rectly connected to one or more inex pensive serial non-volatile rams or eeproms. this pin is shared with th e byte wide interf ace signal, erd#. sda t/s serial data/address. this bidirectional pin is used to transfer addresses and data to or from a serial nvram or eeprom. it is an open drain output and inten ded to be wire-o red with al l other devices on the serial bus using a 4.7k external pull-up resistor. this pin is shared with the byte wide interface signal, ewr#. snv in serial non-volatile device. this input, when high, indicates a serial boot device or no boot device is present. when this pin is low, a byte-wide boot device is present. table 11. byte-wide nv devices signal type description ea[15:00] out external nv memo ry address. these signals connect directly to the ex ternal bios (or eeprom) or eprom address pins ea0 through ea15. the pci in terface controller assembles 32-bit-wide accesses through multiple read cycles of the 8-bit device. the address space from 0040h through 007fh is used to preload and initialize the pci configuration regist ers. should an external nv memory be used, the minimum size required is 128 bytes and the maximum is 64k bytes. when a serial memory is con- nected to the s5335, the pins ea[7:0] are reconfig ured to become a hardware add-on to pci mailbox register with the ea8 pin as the mailbox load clock. also, the ea15 signal pin will provide an indication that the pci to add-on fifo is full (frf#), and the ea14 signal pin will indicate whether the add-on to pci fifo is empty (fwe#). erd# out external nv memory read cont rol. this pin is asserted during re ad operations involving the external non-volatile memory. data is transferred into the s533 5 during the low to high transition of erd#. this pin is shared with the serial external memory interface signal, scl. ewr# t/s external nv memory write control. this pin is asserted during write operations involving the external non-volatile memory. data is presented on pins eq[7:0] along with its a ddress on pins ea[15:0] throughout the entire assertion of ewr#. this pin is shared with the serial external memory interface signal, sda. eq[7:0] t/s external memory data bus. these pins are used to directly connect with the data pins of an external non-volatile memory. when a serial memory is connec ted to the s5335, the pins eq4, eq5, eq6 and eq7 become reconfigured to provide signal pins fo r bus mastering control from the add-on interface. s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 24 data sheet add-on bus interface signals the following sets of signals represent the interface pins available for the add-on function. there are four groups: register access, fifo access, pass-thru mode pins, and general system pins. table 12. register access pins signal type description dq[31:00] t/s datapath dq0?dq31. these pins represent t he datapath for the add-on peripheral?s data bus. they provide the interface to the controller?s fi fo and other registers. when mode = v cc , only dq[15:00] are used. dq[31:0] have intern al 50k ohm pull-up resistors. adr[6:2] in add-on addresses. these signals are the addre ss lines to select which of the 16 dword registers within the controlle r is desired for a given read or writ e cycle, as shown in the table below. adr[6:2] register name 0 0 0 0 0 add-on incoming mailbox reg. 1 0 0 0 0 1 add-on incoming mailbox reg. 2 0 0 0 1 0 add-on incoming mailbox reg. 3 0 0 0 1 1 add-on incoming mailbox reg. 4 0 0 1 0 0 add-on outgoing mailbox reg. 1 0 0 1 0 1 add-on outgoing mailbox reg. 2 0 0 1 1 0 add-on outgoing mailbox reg. 3 0 0 1 1 1 add-on outgoing mailbox reg. 4 01 0 0 0 add-on fifo port 0 1 0 0 1 bus master write address register 01 0 1 0 add-on pass-thru address 01 0 1 1 add-on pass-thru data 0 1 1 0 0 bus master read address register 0 1 1 0 1 add-on mailbox empty/full status 0 1 1 1 0 add-on interrupt control 0 1 1 1 1 add-on general control/status register 1 0 1 1 0 bus master write transfer count 1 0 1 1 1 bus master read transfer count be3# or adr1 in byte enable 3 (32-bit mode) or adr1 (16 bit mode). this pin is used in conjunction with the read or write strobes (rd# or wr#) and th e add-on select signal, select#. as a byte enable, it is neces- sary to have this pin asserted to perform write operations to the register identified by adr[6:2] bit loca- tions d24 through d31; for read operations it controls the dq[31:24] output dr ive. be3# has an internal 50k ohm pull-up resistor. be[2:0]# in byte enable 2 through 0. these pins provide for in dividual byte control during register read or write operations. be2# controls activity over dq[23:dq16], be1# controls dq[15:8], and be0# controls dq[7:0]. during read operations they control the output drive for each of their respective byte lanes; for write operations they serve as a required enable to perform the modification of each byte lane. be[2:0]# have internal 50k ohm pull-up resistors. s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 25 data sheet select# in select for the add-on interface. this signal mu st be driven low for any wr ite or read access to the add- on interface registers. this signal must be st able during the assertion of command signals wr# or rd#. wr# in write strobe. this pin, when asserted in conjunction with the select# pin, causes the writing of one of the internal registers. the s pecific register and operand size are identified through address pins adr[6:2] and the byte enables, be[3:0]#. rd# in read strobe. this pin, when asserted in conjunct ion with the select# pin, causes the reading of one of the internal registers. the s pecific register and operand size are identified through address pins adr[6:2] and the byte enables be[3:0]#. mode in this pin control whether the s5335 data accesses on the dq bus are to be 32-bits wide (mode = low) or 16-bits wide (mode = high). when in the 16 bit m ode, the signal be3# is reassigned as the address signal adr1. mode has an internal 50k ohm pull-up resistor. table 13. fifo access pins signal type description wrfifo# in write fifo. this signal provides a method to directly write the fifo wit hout having to generate the select# signal or the adr[6:2] value of [01000b] to access the fifo. access width is either 32 bits or 16 bits depending on the data bus size available. this signal is intended for implementing pci dma transfers with the add-on syst em. wrfifo# has an internal 50k ohm pull-up resistor. rdfifo# in read fifo. this signal provides a method to directly read the fifo wit hout having to generate the select# signal or the adr[6:2] value of [01000b] to access the fifo. access width is either 32 bits or 16 bits, depending on the data bus size defined by the mode pin. this signal is intended for imple- menting pci dma transfers with the add-on system. rdfifo# has an internal 50k ohm pull-up resis- tor. wrfull out write fifo full. this pin indicates whether the add-on-to-pci bus fifo is ab le to accept more data. this pin is intended to be used to implement dma hardware on the add-on system bus. a logic low output from this pin can be used to repres ent a dma write (add-on to-pci fifo) request. rdempty out read fifo empty. this pin indicates whether the read fifo (pci-to-add-on fifo) contains data. this pin is intended to be used by the add-on syst em to control dma transfers from the pci bus to the add-on system bus. a logic low fr om this pin can be used to repr esent a dma (pci-to-add-on fifo) request. table 14. pass-thru interface pins signal type description ptatn# out pass-thru attention. this signal identifies that an active pci bus cycle has been decoded and data must be read from or written to the pass-thru data register. ptburst# out pass-thru burst. this si gnal identifies pci bus o perations involvi ng the current pa ss-thru cycle as requesting burst access. ptrdy# in pass-thru ready. this i nput indicates when add-on logic has completed a pa ss-thru cycle and another may be initiated. ptnum[1:0] out pass-thru number. these signals identify which of the four base address registers decoded a pass- thru bus activity. these bits are only meaningful when signal ptatn# is active. a value of 00 corre- sponds to base address register 1, a value of 01 for base address register 2, and so on. table 12. register access pins (continued) signal type description s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 26 data sheet ptbe[3:0]# out pass-thru byte enables. these signals indicate which bytes are requested for a given pass-thru operation. they are valid during t he presence of signal ptatn# active. ptadr# in pass-thru address. this signal causes the actual pass-thru requested address to be presented as outputs on the dq pins dq[31:0] for add-ons with 32-bit buses, or the low-order 16 bits for add-ons with 16-bit buses. it is necessary that all other bus control signals be in their inactive state during the assertion of ptadr#. the purpose of this signal is to provide the direct addressing of external add- on peripherals through use of the ptnum[1:0] and the low-order address bits presented on the dq bus with this pin active. ptwr out pass-thru write. this signal identifies whether a pass-thru operation is a read or write cycle. this signal is valid only when ptatn# is active. table 15. system pins signal type description sysrst# out system reset. this low active output is a buffered form of the pci bus reset, rst#. it is not synchro- nized to any clock within the pci interface controller. additionally, this signal can be invoked through software from the pci host interface. bpclk out buffered pci clock. this output is a buffered fo rm of the pci bus clock and, as such, has all of the behavioral characteristics of the pci clock (i.e., dc-to-33 mhz capability). irq# out interrupt. this pin is used to signal the ad d-on system that a significant ev ent has occurred as a result of activity within the pci controller. rsvd in reserved. this pin must be left open at all times. table 14. pass-thru interface pins (continued) signal type description s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 27 data sheet pci configuration registers each pci bus device contains a unique 256-byte region called its configuration header space. portions of this configuration header are mandatory in order for a pci agent to be in full compliance with the pci spec- ification. this secti on describes each of the configuration space fields?i ts address, default values, initialization options, and bi t definitions?and also pro- vides an explanation of its intended usage. table 16. configuration registers configuration address offset abbreviation register name 00h?01h vid vendor identification 02h?03h did device identification 04h?05h pcicmd pci command register 06h?07h pcists pci status register 08h rid revision iden tification register 09h?0bh clcd class code register 0ch caln cache line size register 0dh lat master latency timer 0eh hdr header type 0fh bist built-in self-test 10h?27h badr0-badr5 base address registers (0-5) 28h?2fh ? reserved 30h exrom expansion rom base address 34h?3bh ? reserved 3ch intln interrupt line 3dh intpin interrupt pin 3eh mingnt minimum grant 3fh maxlat maximum latency 40h?ffh ? not used s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 28 data sheet pci configuratio n space header bist 00 04 08 0c 10 14 18 1c 20 24 28 2c 30 34 38 3c 31 23 24 16 15 8 7 latency timer interrupt pin min_gnt max_lat interrupt line expansion rom base address header type = 0 base address register #0 base address register #1 base address register #2 base address register #3 base address register #4 base address register #5 reserved = 0's reserved = 0's reserved = 0's reserved = 0's rev id cache line size vendor id command device id class code status 00 legend note: some registers are a combination of the above. see individual sections for full description. eprom is data source (read only) control function eprom initialized ram (can be altered from pci port) eprom initialized ram (can be altered from add-on port) hard-wired to zeroes s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 29 data sheet vendor identification register (vid) the vid register contains the vendor identification number. this number is assigned by the pci special interest group and is intended to uniquely identify any pci device. write operations from the pci interface have no effect on this register. after reset is removed, this field can be boot-loaded from the external non-vol- atile device (if present and valid) so that other legitimate pci sig members can substitute their ven- dor identification number for this field. figure 7. vendor identification register register name: vendor identification address offset: 00h-01h power-up value: 10e8h (amcc, applied micro cir- cuits corp.) boot-load: external nvram offset 040h-41h attribute: read only (ro) size: 16 bits table 17. vendor id entification register bit description 15:0 vendor identification number: this is a 16 bit-value assigned to amcc. 15 0 10e8h vendor identification register (ro) s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 30 data sheet device identification register (did) the did register contains the vendor-assigned device identification number. this number is generated by amcc in compliance with t he conditions of the pci specification. write operations from the pci interface have no effect on this register. after reset is removed, this field can be boot-loaded from the external non-vol- atile device (if present and valid) so that other legitimate pci sig members can substitute their own device identification number for this field. figure 8. device identification register register name: device identification address offset: 02h-03h power-up value: 4750 (ascii hex for ?gp?, general purpose) boot-load: external nvram offset 042h-43h attribute: read only size: 16 bits table 18. device identification register bit description 15:0 device identificat ion number: this is a 16-bit value initially assigned by amcc for applications using the amcc vendor id. 15 0 device identification register (ro) 4750h s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 31 data sheet pci command register (pcicmd) this 16-bit register contains the pci command. the function of this register is defined by the pci specifica- tion and its implementation is required of all pci devices. only six of the ten fields are used by this device; those which are not used are hardwired to 0. the definitions for all fields are provided here for completeness. figure 9. pci command register register name: pci command address offset: 04h-05h power-up value: 0000h boot-load: not used attribute: read/write (r/w on 6 bits, read only for all others) size: 16 bits 15 0 reserved = 00's fast back-to-back serre wait cycle enable parity error enable palette snoop enable memory write and invalidate enable special cycle enable bus master enable memory access enable i/o access enable x 0000x x x 1 2 3 4 5 6 7 8 9 0x s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 32 data sheet table 19. pci command register bit description 15:10 reserved. equals all 0?s. 9 fast back-to-back enable. the s5335 does not support this func tion. this bit must be set to zero. this bit is cleared to a 0 upon reset#. 8 system error enable. when this bit is set to 1, it permi ts the s5335 controller to dr ive the open drain output pin, serr#. this bit is cleared to 0 upon reset#. the serr# pin driv en active normally signifies a parity error on the address/control bus. 7 wait cycle enable. this bit controls whether this device does address/data stepping. since the s5335 controller never uses stepping, it is hardwired to 0. 6 parity error enable. this bit, when set to a one, allows this controller to check for parity errors. when a parity error is detected, the pci bus signal perr# is asserted. this bit is cleared (parity testing disa bled) upon the assertion of reset#. 5 palette snoop enable. this bit is not supported by the s5335 controller and is hardwired to 0. this feature is used solely for pci-based vga devices. 4 memory write and invalidate enable. this bit allows certai n bus master devices to use the memory write and inval- idate pci bus command when set to 1. when set to 0, ma sters must use the memory write command instead. the s5335 controller does not support this command when oper ated as a master and therefore it is hardwired to 0. 3 special cycle enable. devices which are capable of monitoring special cycles can do so when this bit is set to 1. the s5335 controller does not monitor (or generate) special cycles and this bit is hardwired to 0. 2 bus master enable. this bit, when set to a one, allows th e s5335 controller to function as a bus master. this bit is initialized to 0 upon the assertion of signal pin reset#. 1 memory space enable. this bit allows the s5335 controller to decode and respond as a target for memory regions that may be defined in one of the five base address register s. this bit is initialized to 0 upon the assertion of signal pin reset#. 0 i/o space enable. this bit allows the s5335 controller to decode and respond as a target to i/o cycles which are to regions defined by any one of the five base address registers. this bit is initialized to 0 upon the assertion of signal pin reset#. s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 33 data sheet pci status register (pcists) this 16-bit register contains the pci status informa- tion. the function of this register is defined by the pci specification and its implementation is required of all pci devices. only some of the bits are used by this device; those which are not used are hardwired to 0. most status bits within this register are designated as ?write clear,? meaning that in order to clear a given bit, the bit must be written as a 1. all bits written with a 0 are left unchanged. these bits are identified in figure 10 as (r/wc). those which are read only are shown as (ro) in figure 10. figure 10. pci status register register name: pci status address offset: 06h-07h power-up value: 0080h boot-load: not used attribute: read only (ro), read/write clear (r/wc) size: 16 bits 7 x 0 0 x x x 6 x x reserved (ro) signaled target abort (r/wc) received target abort (r/wc) received master abort (r/wc) signaled system error (r/wc) detected parity error (r/wc) 0 15 14 13 12 11 10 9 8 reserved (ro) = 00's fast back-to-back (ro) data parity reported (r/wc) devsel# timing status (ro) 0 0 = fast (s5335) 0 1 = medium 1 0 = slow 1 1 = reserved s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 34 data sheet table 20. pci status register bit description 15 detected parity error. this bit is set whenever a parity e rror is detected. it functions independently from the state of command register bit 6. this bit may be cleared by writing a 1 to this location. 14 signaled system error. this bit is se t whenever the device asserts the signal serr#. this bit can be reset by writing a 1 to this location. 13 received master abort. this bit is set whenever a bus master abort occurs. this bit can be reset by writing a 1 to this location. 12 received target abort. this bit is set whenever this devi ce has one of its own initiated cycles terminated by the cur- rently addressed target. this bit can be reset by writing a 1 to this location. 11 signaled target abort. this bit is set whenever this device aborts a cycle when addressed as a ta rget. this bit can be reset by writing a 1 to this location. 10:9 device select timing. these bits are read-only and de fine the signal behavior of devsel# from this device when accessed as a target. 8 data parity reported. this bit is set upon the detection of a data parity error for a transfer involving the s5335 device as the master. the parity error enable bit (d6 of the comma nd register) must be set in or der for this bit to be set. once set, it can only be cleared by either writing a 1 to this location or by the assertion of the signal reset#. 7 fast back-to-back capable. when equal to 1, this indicates that the device can accept fast back-to-back cycles as a target. 6:0 reserved. equal all 0?s. s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 35 data sheet revision identification register (rid) the rid register contains the revision identification number. this field is initially cleared. write operations from the pci interface have no effect on this register. after reset is removed, this field can be boot-loaded from the external non-volatile device (if present and valid) so that another value may be used. figure 11. revision identification register register name: revision identification address offset: 08h power-up value: 00h boot-load: external nvram/eprom offset 048h attribute: read only size: 8 bits table 21. revision identification register bit description 7:0 revision identification number. initialized to zeros, this re gister may be loaded to the value in non-volatile memory at offset 048h. 7 0 00h revision identification number (ro) s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 36 data sheet class code register (clcd) this 24-bit, read-only register is divided into three one- byte fields: the base class re sides at location 0bh, the sub-class at 0ah, and the programming interface at 09h. the default setting for the base class is all ones (ffh), which indicates that the device does not fit into the thirteen base classes defined in the pci local bus specification. it is possible , however, through use of the external non-volatile memory, to implement one of the defined class codes described in table 22 below. for devices that fall within the seven defined class codes, sub-classes are al so assigned. tables 23 through 35 describe each of the sub-class codes for base codes 00h through 0ch, respectively. figure 12. class code register register name: class code address offset: 09h-0bh power-up value: ff0000h boot-load: external nvram offset 049h-4bh attribute: read only size: 24 bits table 22. defined base class codes base-class description 00h early, pre-2.0 pci specification devices 01h mass storage controller 02h network controller 03h display controller 04h multimedia device 05h memory controller 06h bridge device 07h simple communication controller 08h base system peripherals 09h input devices 0ah docking stations 0bh processors 0ch serial bus controllers 0d-feh reserved ffh device does not fit defined class codes (default) 7 0 sub-class 7 0 7 0 base class prog i/f (bit) (offset) @09h @0ah @0bh s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 37 data sheet table 23. base class code 00h: earl y, pre-2.0 specification devices sub-class prog i/f description 00h 01h 00h 00h all devices other than vga vga-compatible device table 24. base class code 01h: mass storage controllers sub-class prog i/f description 00h 01h 02h 03h 04h 80h 00h xxh 00h 00h 00h 00h scsi controller ide controller floppy disk controller ipi controller raid controller other mass storage controller table 25. base class code 02h: network controllers sub-class prog i/f description 00h 01h 02h 03h 80h 00h 00h 00h 00h 00h ethernet controller token ring controller fddi controller atm controller other network controller table 26. base class code 03h: display controllers sub-class prog i/f description 00h 00h 01h 80h 00h 01h 00h 00h vga-compatible controller 8514 compatible controller xga controller other display controller table 27. base class code 04h: multimedia devices sub-class prog i/f description 00h 01h 80h 00h 00h 00h video device audio device other multimedia device table 28. base class code 05h: memory controllers sub-class prog i/f description 00h 01h 80h 00h 00h 00h ram memory controller flash memory controller other memory controller s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 38 data sheet table 29. base class code 06h: bridge devices sub-class prog i/f description 00h 01h 02h 03h 04h 05h 06h 07h 80h 00h 00h 00h 00h 00h 00h 00h 00h 00h host/pci bridge pci/isa bridge pci/eisa bridge pci/micro channel bridge pci/pci bridge pci/pcmcia bridge nubus bridge cardbus bridge other bridge type table 30. base class code 07h: simple communications controllers sub-class prog i/f description 00h 00h 01h 02h generic xt compatible serial controller 16450 compatible serial controller 16550 compatible serial controller 01h 00h 01h 02h parallel port bidirectional parallel port ecp 1.x compliant parallel port 80h 00h other communications device table 31. base class code 08h: base system peripherals sub-class prog i/f description 00h 00h 01h 02h generic 8259 pic isa pic eisa pic 01h 00h 01h 02h generic 8237 dma controller isa dma controller eisa dma controller 02h 00h 01h 02h generic 8254 system timer isa system timer eisa system timers (2 timers) 03h 00h 01h generic rtc controller isa rtc controller 80h 00h other system peripheral table 32. base class co de 09h: input devices sub-class prog i/f description 00h 01h 02h 80h 00h 00h 00h 00h keyboard controller digitizer (pen) mouse controller other input controller s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 39 data sheet table 33. base class code 0ah: docking stations sub-class prog i/f description 00h 80h 00h 00h generic docking station other type of docking station table 34. base class code 0bh: processors sub-class prog i/f description 00h 01h 02h 10h 40h 00h 00h 00h 00h 00h intel386? intel486? pentium? alpha? co-processor table 35. base class code 0ch: serial bus controllers sub-class prog i/f description 00 01h 02h 00h 00h 00h firewire? (ieee 1394) access.bus ssa s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 40 data sheet cache line size register (caln) this register is hardwired to 0. the cache line configu- ration register is used by the system to define the cache line size in double-word (64-bit) increments. this controller does not use the ?memory write and invalidate? pci bus cycle commands when operating in the bus master mode, and therefore does not inter- nally require this register. w hen operating in the target mode, this controller does not have the connections necessary to ?snoop? the pci bus and accordingly cannot employ this register in the detection of burst transfers that cross a line boundary. figure 13. cache line size register register name: cache line size address offset: 0ch power-up value: 00h, hardwired boot-load: not used attribute: read only size: 8 bits 7 0 00h cache line size (ro) s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 41 data sheet latency timer register (lat) the latency timer register has meaning only when this controller is used as a bus master and pertains to the number of pci bus clocks that this master will be guar- anteed. the nonzero value for this register is internally decremented after this device has been granted the bus and has begun to assert frame#. prior to this latency timer count reaching zero, this device can ignore the removal of the bus grant and may continue the use of the bus for data transfers. figure 14. latency timer register register name: latency timer address offset: 0dh power-up value: 00h boot-load: external nvram offset 04dh attribute: read/write, bits 7:3; read only bits 2:0 size: 8 bits 7 0 latency timer value (r/w) # of clocks x 8 0 1 0 2 0 3 x 4 x 5 x 6 x x bit value s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 42 data sheet header type register (hdr) this register consists of two fields: bits 6:0 define the format for bytes 10h through 3fh of the device config- uration header, and bit 7 es tablishes whether this device represents a single function (bit 7 = 0) or a mul- tifunction (bit 7 = 1) pc i bus agent. the s5335 is a single function pci device. figure 15. header type register register name: header type address offset: 0eh power-up value: 00h boot-load: external nvram offset 04eh attribute: read only size: 8 bits 7 0 single/multi-function device (read only) 0 = single function 1 = multi-function 1 2 3 4 5 6 x bit value 00h format field (read only) s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 43 data sheet built-in self-test register (bist) the built-in self-test (bist) register permits the implementation of custom, user-specific diagnostics. this register has four fields as depicted in figure 16. bit 7, when set signifies that this device supports a built-in self test. when bit 7 is set, writing a 1 to bit 6 will commence the self test. in actuality, writing a 1 to bit 6 produces an interrupt to the add-on interface. bit 6 will remain set until cleared by a write operation to this register from the add- on bus interface. when bit 6 is reset it is interpreted as completion of the self-test and an error is indicated by a non-zero value for the completion code (bits 3:0). figure 16. built-in self test register register name: built-in self-test address offset: 0fh power-up value: 00h boot-load: external nvram/eprom offset 04fh attribute: d7, d5-0 read only, d6 as pci bus write only size: 8 bits table 36. built-in self-test register bit description 7 bist capable. this bit indicates that the add-on device su pports a built-in self-test when a one is returned. a zero should be returned if this self test feature is not desired. this field is read only from the pci interface. 6 start bist. writing a 1 to this bit indicates that the self-tes t should commence. this bit can only be written when bit 7 is a 1. when bit 6 becomes set, an interrupt is issued to the ad d-on interface. other than thr ough the reset pin, bit 6 can only be cleared by a write to this elem ent from the add-on bus interface as out lined in section 6.5. the pci bus spec- ification requires that this bit be cleared within 2 seconds after being set, or the device will be failed. 5:4 reserved. these bits are reserved. this field will always return zeros. 3:0 completion code. this field provides a method for detailing a device-specific error. it is considered valid when the start bist field (bit 6) changes from 1 to 0. an all-zero va lue for the completion code in dicates successful completion. 7 0 x 1 x 2 x 3 x 4 0 5 0 6 0 x bit value user defined completion code (ro) reserved (ro) start bist (wo) bist capable (ro) s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 44 data sheet base address registers (badr) the base address registers provide a mechanism for assigning memory or i/o space for the add-on func- tion. the actual location(s) the add-on function is to respond to is determined by first interrogating these registers to ascertain the size or space desired, and then writing the high-order field of each register to place it physically in the system?s address space. bit zero of each field is used to select whether the space required is to be decoded as memory (bit 0 = 0) or i/o (bit 0 = 1). since this pci controller has 16 dwords of internal operating registers, the base address reg- ister at offset 10h is assigned to them. the remaining five base address registers can only be used by boot- loading them from the external nvram interface. badr5 register is not im plemented and will return all 0?s. determining base address size the address space defined by a given base address register is determined by wr iting all 1s to a given base address register from the pci bus and then reading that register back. the number of 0s returned starting from d4 for memory space and d2 for i/o space toward the high-order bits reveals the amount of address space desired. tables 39 and 40 list the pos- sible returned values and their corresponding size for both memory and i/o, respectively. included in the table are the nvram/eprom boot values which corre- spond to a given assigned size. a register returning all zeros is disabled. assigning the base address after a base address has been sized as described in the preceding paragraph, the region associated with that base address register (the high order one bits) can physically locate it in memory (or i/o) space. for example, if the fi rst base address register returns ffffffc1h indicating an i/o space (d0=1) and is then written with the value 00000300h. this means that the controller?s internal registers can be selected for i/o addresses between 00000300h through 0000033fh, in this example. the base address value must be on a natural binary boundary for the required size (example 300h, 340h, 380h etc.; 338h would not be allowable). register name: base address address offset: 10h, 14h, 18h, 1ch, 20h, 24h power-up value: ffffffc1h for offset 10h; 00000000h for all others boot-load: external nvram offset 050h, 54h, 58h, 5ch, 60h (badr0-4) attribute: high bits read/write; low bits read only size: 32 bits s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 45 data sheet figure 17. base addr ess register ? memory figure 18. base ad dress register ? i/o 31 30 29 0 x 1 x 2 x 3 x 4 see page 3-157 bit value memory space indicator (ro) 0 = memory 1 = i/o type (ro) 00-locate anywhere (32) 01-below 1 mb 10-locate anywhere (64) 11-reserved programmable (r/w) prefetchable (ro) } 31 0 x 1 0 2bit value i/o space indicator (ro) reserved (ro) programmable (r/w) s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 46 data sheet table 37. base address register ? memory (bit 0 = 0) bit description 31:4 base address location. these bits are used to position the decoded region in memory space. only bits which return a 1 after being written as 1 are usable for this purpose. exce pt for base address register 0, these bits are individually enabled by the contents sourced from the external boot memory. 3 prefetchable. when set as a 1, this bit signifies that th is region of memory can be cached. cachable regions can only be located within the region altered through pci bus memory wr ites. this bit, when set, also implies that all read operations will return the data associated for all bytes regar dless of the byte enables. memory space which cannot support this behavior should leave this bit in the zero stat e. for base addresses 1 through 4, this bit is set by the reset pin and later initialized by the external boot memory (if present). base address register 0 always has this bit set to 0. this bit is read only from the pci interface. 2:1 memory type. these two bits identify whether the memory space is 32 or 64 bits wide and if the space location is restricted to be within the first megabyte of memo ry space. the table below describes the encoding: bits description 2 1 0 0 region is 32 bits wide and can be located anywhere in 32 bit memory space. 0 1 region is 32 bits wide and must be mapped below the first mbyte of memory space. 1 0 region is 64 bits wide and can be mapped anywhere within 64 bit memory space. (not sup- ported by this controller.) 1 1 reserved. (not suppor ted by this controller.) 1 the 64-bit memory space is not supporte d by this controller, so bit 2 should not be set. the only meaningful option is whether it is desired to position memory space anywhere withi n 32-bit memory space or rest rain it to the first mega- byte. for base addresses 1 through 5, this bit is set by the reset pin and later initialized by the external boot memory (if present). 0 space indicator = 0. when set to 0, this bit identifies a base address region as a memory space and the remaining bits in the base address register are defined as shown in table 38. table 38. base address register ? i/o (bit 0 = 1) bit description 31:2 base address location. these bits are used to position the decoded region in i/ o space. only bits which return a ?1? after being written as ?1? are usable for this purpose. except for base address 0, these bits are individually enabled by the contents sourced from the exte rnal boot memory (eprom or nvram). 1 reserved. this bit should be zero. (note: disabled base address registers will return all zeros for the entire register location, bits 31 through 0). 0 space indicator = 1. when one this bit identifies a base addr ess region as an i/o space and the remaining bits in the base address register have the definition as shown in figure 18. s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 47 data sheet 1. the two most significant bits define bus width for badr1:4 in pass-thru operation). 2. bits d3, d2 and d1 may be set to indicate other attributes for the memory space. see text for details. 3. badr5 register is not implemented and will return all 0?s. table 39. read response (memory assigned) to an all- ones write operation to a base address register response size in bytes [eprom boot value] 1 00000000h fffffff0h ffffffe0h ffffffc0h ffffff80h ffffff00h fffffe00h fffffc00h fffff800h fffff000h ffffe000h ffffc000h ffff8000h ffff0000h fffe0000h fffc0000h fff80000h fff00000h ffe00000h ffc00000h ff800000h ff000000h fe000000h fc000000h f8000000h f0000000h e0000000h none - disabled 16 bytes (4 dwords) 32 bytes (8 dwords) 64 bytes (16 dwords) 128 bytes (32 dwords) 256 bytes (64 dwords) 512 bytes (128 dwords) 1k bytes (256 dwords) 2k bytes (512 dwords) 4k bytes (1k dwords) 8k bytes (2k dwords) 16k bytes (4k dwords) 32k bytes (8k dwords) 64k bytes (16k dwords) 128k bytes (32k dwords) 256k bytes (64k dwords) 512k bytes (128k dwords) 1m bytes (256k dwords) 2m bytes (512k dwords) 4m bytes (1m dwords) 8m bytes (2m dwords) 16m bytes (4m dwords) 32m bytes (8m dwords) 64m bytes (16m dwords) 128m bytes (32m dwords) 256m bytes (64m dwords) 512m bytes (128m dwords) 00000000h or bios missing 2,3 fffffff0h ffffffe0h ffffffc0h ffffff80h ffffff00h fffffe00h fffffc00h fffff800h fffff000h ffffe000h ffffc000h ffff8000h ffff0000h fffe0000h fffc0000h fff80000h fff00000h ffe00000h ffc00000h ff800000h ff000000h fe000000h fc000000h f8000000h f0000000h e0000000h s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 48 data sheet 1. badr5 register is not implemented and will return all 0?s. 2. base address register 0 (at offset) 10h powers up as ffffffc1h. this default assignment allows usage without an external boot memory. should an eprom or nvram be used, the base address can be boot loaded to become a memory spac e (ffffffc0h or ffffffc2h). table 40. read response (i/o assigned) to an all- ones write operation to a base address register response size in bytes [eprom boot value] 00000000h fffffffdh fffffff9h fffffff1h ffffffe1h ffffffc1h ffffff81h ffffff01h none - disabled 4 bytes (1 dwords) 8 bytes (2 dwords) 16 bytes (4 dwords) 32 bytes (8 dwords) 64 bytes (16 dwords) 128 bytes (32 dwords) 256 bytes (64 dwords) 00000000h or bios missing 1 fffffffdh fffffff9h fffffff1h ffffffe1h ffffffc1h 2 ffffff81h ffffff01h s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 49 data sheet expansion rom base address register (xrom) the expansion base address rom register provides a mechanism for assigning a space within physical memory for an expansion rom. access from the pci bus to the memory space defined by this register will cause one or more accesses to the s5335 controllers? external bios rom (or nvram) interface. since pci bus accesses to the rom may be 32 bits wide, repeated operations to t he rom are generated by the s5335 and the wider data is assembled internal to the s5335 controller and then transferred to the pci bus by the s5335. figure 19. expansion rom base address register register name: expansion rom base address address offset: 30h power-up value: 00000000h boot-load: external nvram offset 70h attribute: bits 31:11, bit 0 read/write; bits 10:1 read only size: 32 bits table 41. expansion rom base address register bit description 31:11 expansion rom base address location. these bits are us ed to position the decoded region in memory space. only bits which return a 1 after being written as 1 are usable fo r this purpose. these bits are individually enabled by the contents sourced from the external boot memory (eprom or nvram). the desired size for the rom memory is determined by writing all ones to this register and then re ading back the contents. the number of bits returned as zeros, in order from least significant to most significant bit, indi cates the size of the expansion rom. this controller limits the expansion rom area to 64k bytes. the allowable re turned values after all ones are written to this register are shown in ttable 42. 10:1 reserved. all zeros. 0 address decode enable. the expansion rom address decoder is enabled or disabled with this bit. when this bit is set, the decoder is enabled; when this bit is zero, the decode r is disabled. it is required that the pci command regis- ter also have the memory decode enabled for this bit to have an effect. 31 0 0 0 1 10 bit value address decode enable (rw) 0=disabled 1=enabled reserved (ro) programmable (r/w) 11 s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 50 data sheet table 42. read response to expansion rom base address register (after all-ones written) response size in bytes [eprom boot value] 00000000h fffff801h fffff001h ffffe001h ffffc001h ffff8001h ffff0001h none - disabled 2k bytes (512 dwords) 4k bytes (1k dwords) 8k bytes (2k dwords) 16k bytes (4k dwords) 32k bytes (8k dwords) 64k bytes (16k dwords) 00000000h or bios missing fffff801h fffff001h ffffe001h ffffc001h ffff8001h ffff0001h s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 51 data sheet interrupt line register (intln) this register indicates the interrupt routing for the s5335 controller. the ultimate value for this register is system-architecture specific. for x86 based pcs, the values in this register correspond with the established interrupt numbers associated with the dual 8259 con- trollers used in those ma chines. in x86-based pc systems, the values of 0 to 15 correspond with the irq numbers 0 through 15, and the values from 16 to 254 are reserved. the value of 255 (the controller?s default power-up value) signifies either ?unknown? or ?no con- nection? for the system interrupt. this register is boot- loaded from the external boot memory, if present, and may be written by the pci interface. figure 20. interrupt line register register name: interrupt line address offset: 3ch power-up value: ffh boot-load: external nvram offset 7ch attribute: read/write size: 8 bit 7 0 1 ffh 5bit value 6432 s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 52 data sheet interrupt pin register (intpin) this register identifies which pci interrupt, if any, is connected to the controller?s pci interrupt pins. the allowable values are 0 (no interrupts), 1 (inta#), 2 (intb#), 3 (intc#), and 4 (intd#). the default power- up value assumes inta#. figure 21. interrupt pin register register name: interrupt pin address offset: 3dh power-up value: 01h boot-load: external nvram offset 7dh attribute: read only size: 8 bits 7 0 1 5 bit value 643 00 0 0 0x x x res er v ed (all zeroes-ro) pin number 0 0 0 none 0 0 1 inta# 0 1 0 intb# 0 1 1 intc# 1 0 0 intd# 1 0 1 reserved 1 1 x reserved 2 s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 53 data sheet minimum grant register (mingnt) this register may be optiona lly used by bus masters to specify how long a burst period the device needs. a value of zero indicates that the bus master has no stringent requirement. the units defined by the least significant bit are in 250-ns in crements. this register is treated as ?information only? and has no further imple- mentation within this device. values other than zero are possible when an extern al boot memory is used. figure 22. minimum grant register register name: minimum grant address offset: 3eh power-up value: 00h boot-load: external nvram offset 7eh attribute: read only size: 8 bits 7 0 value x 250ns (ro) 00-no requirement 01-ffh 1 2 3 4 5 6 0 bit value 000000 0 s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 54 data sheet maximum latency register (maxlat) this register may be optiona lly used by bus masters to specify how often this devi ce needs pci bus access. a value of zero indicates that the bus master has no stringent requirement. the units defined by the least significant bit are in 250-ns in crements. this register is treated as ?information only? and has no further imple- mentation within this device. values other than zero are possible when an extern al boot memory is used. figure 23. maximum latency register register name: maximum latency address offset: 3fh power-up value: 00h boot-load: external nvram offset 7fh attribute: read only size: 8 bits 7 0 value x 250ns (ro) 00-no requirement 01-ffh 1 2 3 4 5 6 0 bit value 000000 0 s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 55 data sheet the pci bus operation registers are mapped as 16 consecutive dword registers located at the address space (i/o or memory) specified by the base address register 0. these locations are the primary method of communication between the pci and add-on buses. data, software-defined commands and command parameters can be either exchanged through the mail- boxes, transferred through the fifo in blocks under program control, or transfe rred using the fifos under bus master control. table 43 lists the pci bus opera- tion registers. table 43. operation registers ? pci bus address offset abbreviation register name 00h omb1 outgoing mailbox register 1 04h omb2 outgoing mailbox register 2 08h omb3 outgoing mailbox register 3 0ch omb4 outgoing mailbox register 4 10h imb1 incoming mailbox register 1 14h imb2 incoming mailbox register 2 18h imb3 incoming mailbox register 3 1ch imb4 incoming mailbox register 4 20h fifo fifo register port (bidirectional) 24h mwar master write address register 28h mwtc master write transfer count register 2ch mrar master read address register 30h mrtc master read transfer count register 34h mbef mailbox empty/full status 38h intcsr interrupt control/status register 3ch mcsr bus master control/status register s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 56 data sheet outgoing mailbox registers (omb) register names: outgoing mailboxes 1-4 these four dword registers provide a method for sending command or parameter data to the add-on system. pci bus operations to these regis- ters may be in any width (byte, word, or dword). writing to these regis- ters can be a source for add-on bus interrupts (if desired) by enabling their interrupt generation through the use of the add-on?s interrupt con- trol/status register. pci address offset: 00h, 04h, 08h, 0ch power-up value: xxxxxxxxh attribute: read/write size: 32 bits incoming mailbox registers (imb) register names: incoming mailboxes 1-4 these four dword regi sters provide a method for receiving user defined data from the add-on system. pci bus read oper ations to these registers may be in any width (byte, word, or dword). only read opera- tions are supported. reading from t hese registers can optionally cause an add-on bus interrupt (if desired) by enabling their interrupt generation through the use of the add-on?s interr upt control/status register. mailbox 4, byte 3 only exists as device pins on the s5335 devices when used with a serial nonvolatile memory. pci address offset: 10h, 14h, 18h, 1ch power-up value: xxxxxxxxh attribute: read only size: 32 bits fifo register port (fifo) register name: fifo port this location provides access to the bidirectional fifo. separate regis- ters are used when reading from or writ ing to the fifo. accordingly, it is not possible to read what was written to this location. the fifo registers are implicitly involved in all bus mast er operations and, as such, should not be accessed during active bus master transfers. when operating upon the fifos with software program transfers involving word or byte operations, the endian sequence of the fifo should be established as described under fifo endian conversion management in order to pre- serve the internal fifo data ordering and flag management. the fifo?s fullness may be observed by reading the master control-status register or mcsr register. pci address offset: 20h power-up value: xxxxxxxxh attribute: read/write size: 32 bits s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 57 data sheet pci controlled bus master write address register (mwar) this register is used to establish the pci address for data moving from the add-on bus to the pci bus dur- ing pci bus memory write operations. it consists of a 30-bit counter with the low-order two bits hardwired as zeros. transfers may be any non-zero byte length as defined by the transfer count register, mwtc, and must begin on a dword boundary. this dword boundary starting constraint is placed upon this con- troller?s pci bus master tr ansfers so that byte lane alignment can be maintained between the s5335 con- troller?s internal fifo data path, the add-on interface, and the pci bus. note: applications which require a non-dword start- ing boundary will need to move the first few bytes under software program control (and without using the fifo) to establish a dword boundary. after the dword boundary is established the s5335 can begin the task of pci bus master data transfers. the master write address register is continually updated during the tr ansfer process a nd will always be pointing to the next unwritte n location. reading of this register during a transfer process (done when the s5335 controller is functioning as a target, i.e. not a bus master) is permitted and may be used to monitor the progress of the transfer . during the address phase for bus master write transfers, the two least significant bits presented on the pci bu s pins ad[31:0] will always be zero. this identifi es to the target memory that the burst address sequen ce will be in a linear order rather than in an intel 486 or pentium? cache line fill sequence. also, the pci bus address bit a1 will always be zero when this controller is the bus master. this signifies to the target that the s5335 controller is burst capable and that the ta rget should not arbitrarily disconnect after the first data phase of this operation. under certain circumstances, mwar can be accessed from the add-on bus instead of the pci bus. see add- on initiated bus mastering. figure 24. pci controlled bus master write address register register name: master write address pci address offset: 24h power-up value: 00000000h attribute: read/write size: 32 bits 31 0 0 1 0 2bit value dword address (ro) write transfer address (r/w) s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 58 data sheet pci controlled bus master write transfer count register (mwtc) the master write transfer count register is used to con- vey to the s5335 controller the actual number of bytes that are to be transferred. the value in this register is decremented with each bus master pci write opera- tion until the transfer count reaches zero. upon reaching zero, the transfer operation ceases and an interrupt may be optionally generated to either the pci or add-on bus interface. transfers which are not whole multiples of dwords in size result in a partial word ending cycle. this partial word ending cycle is possible since all bus master transfers for this control- ler are required to begin on a dword boundary. under certain circumstances, mwtc can be accessed from the add-on bus instead of the pci bus. see add- on initiated bus mastering. figure 25. pci controlled bus mast er write transfer count register register name: master write transfer count pci address offset: 28h power-up value: 00000000h attribute: read/write size: 32 bits 31 0 25 bit value transfer count in bytes (r/w) reserved = o's (ro) 26 00 s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 59 data sheet pci controlled bus master read address register (mrar) this register is used to establish the pci address for data moving to the add-on bus from the pci bus dur- ing pci bus memory read operations. it consists of a 30-bit counter with the low-order two bits hardwired as zeros. transfers may be any non-zero byte length as defined by the transfer count register, mrtc (section 5.7) and must begin on a dword boundary. this dword boundary starting constraint is placed upon this controller?s pci bus mast er transfers so that byte lane alignment can be maintained between the s5335 controller?s internal fifo data path, the add-on inter- face and the pci bus. note: applications which require a non-dword start- ing boundary will need to move the first few bytes under software program control (and without using the fifo) to establish a dword boundary. after the dword boundary is established the s5335 can begin the task of pci bus master data transfers. the master read address register is continually updated during the tr ansfer process a nd will always be pointing to the next unread location. reading of this register during a transfer process (done when the s5335 controller is functioning as a target?i.e., not a bus master) is permitted and may be used to monitor the progress of the transfer . during the address phase for bus master read transfer s, the two least significant bits presented on the pci bus ad[31:0] will always be zero. this identifies to the target memory that the burst address sequence will be in a linear order rather than in an intel 486 or pentium? cache line fill sequence. also, the pci bus address bit a1 will always be zero when this controller is the bus master. this signifies to the target that the controlle r is burst capable and that the target should not arbi trarily disconnect after the first data phase of this operation. under certain circumstances, mrar can be accessed from the add-on bus instead of the pci bus. figure 26. pci controlled bus master read address register register name: master read address pci address offset: 2ch power-up value: 00000000h attribute: read/write size: 32 bits 31 0 0 1 0 2bit value dword address (ro) read transfer address (r/w) s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 60 data sheet pci controlled bus master read transfer count register (mrtc) the master read transfer count register is used to con- vey to the pci controller the actual number of bytes that are to be transferred. the value in this register is decremented with each bus master pci read opera- tion until the transfer count reaches zero. upon reaching zero, the transfer operation ceases and an interrupt may be optionally generated to either the pci or add-on bus interface. transfers which are not whole multiples of dwords in size result in a partial word ending cycle. this partial word ending cycle is possible since all bus master transfers for this control- ler are required to begin on a dword boundary. under certain circumstances, mrtc can be accessed from the add-on bus instead of the pci bus. figure 27. pci controlled bus master read transfer count register register name: master read transfer count pci address offset: 30h power-up value: 00000000h attribute: read/write size: 32 bits 31 0 25 bit value transfer count in bytes (r/w) reserved = 0's (ro) 26 00 s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 61 data sheet mailbox empty full/status register (mbef) this register provides empty /full visibility of each byte within the mailboxes. the empty/full status for the out- going mailboxes is displayed on the low-order 16 bits and the empty/full status for the incoming mailboxes is presented on the high-order 16 bits. a value of 1 signi- fies that a given mailbox has been written by one bus interface but has not yet be en read by the correspond- ing destination interface. a pci bus incoming mailbox is defined as one in which data travels from the add- on bus into the pci bus, and an outgoing mailbox is defined as one where data travels out from the pci bus to the add-on interface. figure 28. mailbox empty/full status register register name: mailbox empty/full status pci address offset: 34h power-up value: 00000000h attribute: read only size: 32 bits 31 0 15 bit value outgoing mailbox status (ro) incoming mailbox status (ro) 16 s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 62 data sheet table 44. mailbox empt y/full status register bit description 31:16 incoming mailbox status. this field indicates which incoming mailbox registers have been written by the add-on interface but have not yet been read by the pci bus. each bi t location corresponds to a specific byte within one of the four incoming mailboxes. a value of one for each bit sign ifies that the specified mailbox byte is full, and a value of zero signifies empty. the mapping of these stat us bits to bytes within each mailbox is as follows: bit 31 = incoming mailbox 4 byte 3 bit 30 = incoming mailbox 4 byte 2 bit 29 = incoming mailbox 4 byte 1 bit 28 = incoming mailbox 4 byte 0 bit 27 = incoming mailbox 3 byte 3 bit 26 = incoming mailbox 3 byte 2 bit 25 = incoming mailbox 3 byte 1 bit 24 = incoming mailbox 3 byte 0 bit 23 = incoming mailbox 2 byte 3 bit 22 = incoming mailbox 2 byte 2 bit 21 = incoming mailbox 2 byte 1 bit 20 = incoming mailbox 2 byte 0 bit 19 = incoming mailbox 1 byte 3 bit 18 = incoming mailbox 1 byte 2 bit 17 = incoming mailbox 1 byte 1 bit 16 = incoming mailbox 1 byte 0 15:00 outgoing mailbox status. this field indicates which out going mail box registers have been written by the pci bus interface but have not yet been read by the add-on bus. each bit location corresponds to a specific byte within one of the four outgoing mailboxes. a value of one for each bit si gnifies that the specified mailb ox byte is full, and a value of zero signifies empty. the mapping of these stat us bits to bytes within each mailbox is as follows: bit 15 = outgoing mailbox 4 byte 3 bit 14 = outgoing mailbox 4 byte 2 bit 13 = outgoing mailbox 4 byte 1 bit 12 = outgoing mailbox 4 byte 0 bit 11 = outgoing mailbox 3 byte 3 bit 10 = outgoing mailbox 3 byte 2 bit 09 = outgoing mailbox 3 byte 1 bit 08 = outgoing mailbox 3 byte 0 bit 07 = outgoing mailbox 2 byte 3 bit 06 = outgoing mailbox 2 byte 2 bit 05 = outgoing mailbox 2 byte 1 bit 04 = outgoing mailbox 2 byte 0 bit 03 = outgoing mailbox 1 byte 3 bit 02 = outgoing mailbox 1 byte 2 bit 01 = outgoing mailbox 1 byte 1 bit 00 = outgoing mailbox 1 byte 0 s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 63 data sheet interrupt control/status register (intcsr) this register provides the method for choosing which conditions are to produce an interrupt on the pci bus interface, a method for viewing the cause of the inter- rupt, and a method for acknowledging (removing) the interrupt?s assertion. interrupt sources: ? write transfer terminal count = zero ? read transfer terminal count = zero ? one of the outgoing mailboxes (1,2,3 or 4) becomes empty ? one of the incoming mailboxes (1,2,3 or 4) becomes full. ? target abort ? master abort figure 29. interrupt control/status register register name: interrupt control and status pci address offset: 38h power-up value: 00000000h attribute: read/write (r/w), read/ write_one_clear (r/wc) size: 32 bits 31 0 15 14 12 8 4 bit value 16 21 23 24 fifo and endian control 0 read transfer complete (r/wc) write transfer complete (r/wc) incoming mailbox interrupt (r/wc) outgoing mailbox interrupt (r/wc) interrupt asserted (ro) target abort (r/wc) master abort (r/wc) 00 0 0 d4-d0 outgoing mailbox (goes empty) d4=enable interrrupt d3-d2=mailbox # 0 0=mailbox 1 0 1=mailbox 2 1 0=mailbox 3 1 1=mailbox 4 d1-d0=byte # 0 0=byte 0 0 1=byte 1 1 0=byte 2 1 1=byte 3 d12-d8 incoming mailbox (r/w) (becomes full) d12=enable interrupt d11-d10=mailbox 0 0=mailbox 1 0 1=mailbox 2 1 0=mailbox 3 1 1=mailbox 4 d9-d8=byte # 0 0=byte 0 0 1=byte 1 1 0=byte 2 1 1=byte 3 interrupt on write transfer complete interrupt on read transfer complete interrupt source (r/w) enable & selection actual interrupt interrupt selection s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 64 data sheet figure 30. fifo management and endian control byte 0 0 1 1 0 no conversion (default) 1 16 bit endian conv. 0 32 bit endian conv. 1 64 bit endian conv fifo advance control pci interface 0 0 byte 0 (default) 0 1 byte 1 1 0 byte 2 1 1 byte 3 fifo advance control add-on interface 0 0 byte 0 (default) 0 1 byte 1 1 0 byte 2 1 1 byte 3 outbound fifo pci add-on dword toggle 0 = bytes 0-3 (default) 1 = byte 4-7 (note1) inbound fifo add-on pci dword toggle 0 = bytes 0-3 (default) 1 = byte 4-7 note 1: d24 and d25 must be also "1" 31 30 29 28 27 26 25 24 1 s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 65 data sheet table 45. interrupt control/status register bit description 31:24 fifo and endian control. 23 interrupt asserted. this read only stat us bit indicates that one or more of the four possible interrupt conditions is present. this bit is nothing more than the oring of the in terrupt conditions described by bits 19 through 16 of this register. 22 reserved. always zero. 21 target abort. this bit signifies that an interrupt has been generated due to the s5335 encountering a target abort during a pci bus cycle while the s5335 wa s the current bus master. this bit ope rates as read or write one clear. a write to this bit with the data of ?one? will cause this bit to be reset, a write to this bit with the data of ?zero? will not change the state of this bit. 20 master abort. this bit signifies that an interrupt has been generated due to the s5335 encountering a master abort on the pci bus. a master abort occurs when there is no target re sponse to a pci bus cycle. this bit operates as read or write one clear. a write to this bit with the data of ?one? will cause this bi t be reset, a write to this bit with the data of ?zero? will not change the state of this bit. 19 read transfer complete. this bit signifies that an interru pt has been generated due to the completion of a pci bus master operation involving the transfer of data from the pci bus to the add-on. this interrupt will occur when the master read transfer count register reaches zero. this bit operates as read or write one clear. a write to this bit with the data of ?one? will cause this bit to be reset; a write to this bit with the data of ?zero? will not change the state of this bit. 18 write transfer complete. this bit signifies that an inte rrupt has been generated due to the completion of a pci bus master operation involving the transfer of data to the pc i bus from the add-on. this interrupt will occur when the master write transfer count register reaches zero. this bit operates as read or write one clear. a write to this bit with the data of ?one? will cause this bit to be reset; a write to this bit with the data of ?zero? will not change the state of this bit. 17 incoming mailbox interrupt. this bit is set when the mailbox selected by bits 12 through 8 of this register are written by the add-on interface. this bit operates as read or wr ite one clear. a write to this bit with the data of ?one? will cause this bit to be reset; a write to this bit with t he data as ?zero? will not c hange the state of this bit. 16 outgoing mailbox interrupt. this bit is set when the mailbox selected by bits 4 through 0 of this register is read by the add-on interface. this bit operates as read or write one clea r. a write to this bit with the data of ?one? will cause this bit to be reset; a write to this bit with the data of ?zero? will not change the state of this bit. 15 interrupt on read transfer complete. this bit enables the occurrence of an interrupt w hen the read transfer count reaches zero. this bit is read/write. 14 interrupt on write transfer complete. this bit enables t he occurrence of an interrupt when the write transfer count reaches zero. this bit is read/write. 13 reserved. always zero. 12 enable incoming mailbox interrupt. this bit allows a write from the incoming mailbox register identified by bits 11 through 8 to produce a pci interface interrupt. this bit is read/write. 11:10 incoming mailbox interrupt select. th is field selects which of the four incoming mailboxes is to be the source for causing an incoming mailbox interrupt. [00]b selects mailbox 1, [01]b selects mailbox 2, [10]b selects mailbox 3 and [11]b selects mailbox 4. this field is read/write. 9:8 incoming mailbox byte interrupt select. this field selects which byte of the mailbox selected by bits 10 and 11 above is to actually cause the interrupt. [00] b selects byte 0, [01]b selects byte 1, [10]b selects byte 2, and [11]b selects byte 3. this fiel d is read/write. 7:5 reserved, always zero. s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 66 data sheet 4 enable outgoing mailbox interrupt. this bit allows a read by the add-on of the outgoing ma ilbox register identified by bits 3 through 0 to produce a pci interface interrupt. this bit is read/write. 3:2 outgoing mailbox interrupt select. this field selects whic h of the four outgoing mailboxes is to be the source for causing an outgoing mailbox interrupt. [00]b selects mail box 1, [01]b selects mailbox 2, [10]b selects mailbox 3 and [11]b selects mailbox 4. this field is read/write. 1:0 outgoing mailbox byte interrupt select. this field selects wh ich byte of the mailbox selected by bits 3 and 2 above is to actually cause the interrupt. [00]b sele cts byte 0, [01]b selects byte 1, [10] b selects byte 2, and [11]b selects byte 3. this field is read/write. table 45. interrupt control/status register (continued) bit description s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 67 data sheet master control/statu s register (mcsr) this register provides for overall control of this device. it is used to enable bus mastering for both data direc- tions as well as providing a method to perform software resets. the following pci bus controls are available: ? write priority over read ? read priority over write ? write transfer enable ? write master requests on 4 or more fifo words available (full) ? read transfer enable ? read master requests on 4 or more fifo avail- able (empty) ? assert reset to add-on ? reset add-on to pci fifo flags ? reset pci to add-on fifo flags ? reset mailbox empty full status flags ? write external non-volatile memory the following pci interface status flags are provided: ? pci to add-on fifo full ? pci to add-on fifo has four or more empty locations ? pci to add-on fifo empty ? add-on to pci fifo full ? add-on to pci fifo has four or more words loaded ? add-on to pci fifo empty ? pci to add-on transfer count = zero ? add-on to pci transfer count = zero figure 31. bus master control/status register register name: master control/status pci address offset: 3ch power-up value: 000000e6h attribute: read/write, read only, write only size: 32 bits 31 29 27 24 23 0 14 12 10 8 7 6 5 15 bit value fifo status (ro) d5=add-on to pci fifo empty d4=add-on to pci fifo 4+ words d3=add-on to pci fifo full d2=pci to add-on fifo empty d1=pci to add-on fifo 4+spaces d0=pci to add-on fifo full d7=add-on to pci transfer count equals zero (r0) d6=pci to add-on transfer count equals zero (r0) 16 0 write transfer control (r/w) (pci memory writes) d10=write transfer enable d9=fifo management scheme d8=write vs read priority reset controls (r/wc) d27=mailbox flags reset d26=add-on to pci fifo status flags reset d25=pci to add-on fifo status flags reset d24=add-on reset nv operation address/data memory read multiple enable = 1 disable = 0 read transfer control (r/w) (pci memory reads) d14=read transfer enable d13=fifo management scheme d12=read vs. write priority nvram access ctrl 0 0 control status s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 68 data sheet table 46. bus master control/status register bit description 31:29 nvram access control. this field provides a method fo r access to the optional external non-volatile memory. write operations are achieved by a sequence of byte operations involving these bits and the 8-bit field of bits 23 through 16. the sequence requires that the low- order address, high order address, and then a data byte are loaded in order. bit 31 of this field acts as a combined enable and ready for the access to the external memory. d31 must be written to a 1 before an access can begin, and subsequent access es must wait for bit d31 to become zero (ready). d31 d30 d29 w/r 0 x x w inactive 1 0 0 w load low address byte 1 0 1 w load high address byte 1 1 0 w begin write 1 1 1 w begin read 0 x x r ready 1 x x r busy cautionary note: the nonvolatile memory interface is also available for access by the add-on interface. accesses by both the add-on and pci bus to the nv memory are not directly supported by the s5335 device. software must be designed to prevent the simultaneous access of nv memory to prevent data corruption within the memory and provide for accurate data retrieval. 28 fifo loop back mode. 27 mailbox flag reset. writing a one to this bit causes all mailb ox status flags to become re set (empty). it is not nec- essary to write this bit as zero because it is used internally to produce a re set pulse. since reading of this bit will always produce zeros, this bit is write only. 26 add-on to pci fifo status reset. writ ing a one to this bit causes the add-on to pci (bus master memory writes) fifo empty flag to set indicating empty and the fifo full flag to reset and the fifo four plus word flag to reset. it is not necessary to write this bit as zero because it is used internally to produce a reset pulse. since reading of this bit will always produce zeros, this bit is write only. 25 pci to add-on fifo status reset. writ ing a one to this bit causes the pci to add-on (bus master memory reads) fifo empty flag to set indicating empty and the fifo fu ll flag to reset and the fifo four plus words available flag to set. it is not necessary to writ e this bit as zero because it is used in ternally to produce a reset pulse. since reading of this bit will always produce zeros, this bit is write only. 24 add-on pin reset. writing a one to this bit causes the reset output pin to become active. writing a zero to this pin is necessary to remove the a ssertion of reset. this register bit is read/write. 23:16 non-volatile memory address/data port. th is 8-bit field is used in conjunction with bit 31, 30 and 29 of this register to access the external non-volatile memory. the contents wr itten are either low address, high address, or data as defined by bits 30 and 29. this register will contain the external non-volatile memory data when the proper read sequence for bits 31 through 29 is performed. 15 enable memory read multiple during s5335 bus mastering mode. 14 read transfer enable. this bit must be set to a one for s5335 pci bus master read transfers to take place. writing a zero to this location will suspend an active transfer. an active transfer is one in which the transfer count is not zero. 13 read fifo management scheme. when set to a 1, this bit causes the controller to refrain from requesting the pci bus unless it has four or more vacant fi fo locations to fill. once the controller is granted the pci bus or is in pos- session of the bus due to the write channel, this constraint is not meaningf ul. when this bit is zero the controller will request the pci bus if it has at least one vacant fifo word. s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 69 data sheet 12 read versus write priority. this bit contro ls the priority of read transfers over write transfers. when set to a 1 with bit d8 as zero this indicates that read transfers always have priority over write transfers; when set to a one with d8 as one, this indicates that transfer priorities will alternate equally between read and writes. 11 reserved. always zero. 10 write transfer enable. this bit must be set to a one for pc i bus master write transfers to take place. writing a zero to this location will suspend an active transfer. an active transfer is one in which the transfer count is not zero. 9 write fifo management scheme. when set to a one this bit causes the cont roller to refrain from requesting the pci bus unless it has four or more fifo locations filled. once the s5335 controller is granted the pci bus or is in pos- session of the bus due to the write channel, this constraint is not meaningf ul. when this bit is zero the controller will request the pci bus if it has at least one valid fifo word. 8 write versus read priority. this bit controls the priority of write transfers over read tran sfers. when set to a one with bit d12 as zero this indicates that write transfers always hav e priority over read transfers. this combination is not allowed, data integrity may be compromised. when set to a one with d12 as one, this indicates that transfer priori- ties will alternate equally between writes and reads. 7 add-on to pci transfer count equal zero (ro). this bit is a one to signify that the write transfer count is all zeros. 6 pci to add-on transfer count equals zero (ro). this bit is a one to signify that the read transfer count is all zeros. 5 add-on to pci fifo empty. this bit is a one when the add-on to pci bus fifo is completely empty. 4 add-on to pci 4+ words. this bit is a one when there are four or more fifo words valid within the add-on to pci bus fifo. 3 add-on to pci fifo full. this bit is a one when the add-on to pci bus fifo is completely full. 2 pci to add-on fifo empty. this bit is a one wh en the pci bus to add-on fifo is completely empty. 1 pci to add-on fifo 4+ spaces. this bit signifies that th ere are at least four empty words within the pci to add-on fifo. 0 pci to add-on fifo full. this bit is a one when the pci bus to add-on fifo is completely full. table 46. bus master control/status register (continued) bit description s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 70 data sheet add-on bus operation registers the add-on bus interface provides access to 18 dwords (72 bytes) of data, control and status infor- mation. all of these locations are accessed by asserting the add-on bus chip select pin (select#) in conjunction with either the read or write control strobes (signal pin rd# or wr#). access to the fifo can also be achieved through use of the dedicated pins, rdfifo# and wrfifo#. the dedicated pins for control of the fifo are pr ovided to optionally imple- ment direct memory access (dma) on the add-on bus, or to connect with an external fifo. this register group represents the primary method for communication between the add-on and pci buses as viewed by the add-on . the flexibility of this arrangement allows a number of user-defined soft- ware protocols to be built. for example, data, software assigned commands, and command parameters can be exchanged between the pci and add-on buses using either the mailboxes or fifos with or without handshaking interrupts. the register structure is very similar to that of the pci operation register set. the major difference between the pci bus and add-on bus register complement are the absence of bus mas- ter control registers (4) on the add-on side and the addition of two ?pass-through? registers. table 47 lists the add-on interface registers. 1. see add-on initiated bus mastering. table 47. operation registers ? add-on interface address abbreviation register name 00h aimb1 add-on incoming mailbox register #1 04h aimb2 add-on incoming mailbox register #2 08h aimb3 add-on incoming mailbox register #3 0ch aimb4 add-on incoming mailbox register #4 10h aomb1 add-on outgoing mailbox register #1 14h aomb2 add-on outgoing mailbox register #2 18h aomb3 add-on outgoing mailbox register #3 1ch aomb4 add-on outgoing mailbox register #4 20h afifo add-on fifo port 24h mwar 1 bus master write address register 28h apta add-on pass-through address 2ch aptd add-on pass-through data 30h mrar 1 bus master read address register 34h ambef add-on mailbox empty/full status 38h aint add-on interrupt control 3ch agcsts add-on general c ontrol and status register 58h mwtc 1 bus master write transfer count 5ch mrtc 1 bus master read transfer count s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 71 data sheet add-on incoming mailbox registers (aimbx) register names: add-on incoming mailboxes 1-4 these four dword registers pr ovide a method for receiving data, commands, or command pa rameters from the pci inter- face. add-on read operations to these registers may be in any width (byte, word, or dword). these registers are read-only. writes to this address space have no effect. reading from one of these registers can optionally cause a pci bus interrupt (if desired) when the pci interrupt c ontrol/status register is prop- erly configured. add-on address offset: 00h, 04h, 08h, 0ch power-up value: xxxxxxxxh attribute: read only size: 32 bits add-on outgoing mailbox registers (aombx) register names: add-on outgoing mailboxes 1-4 these four dword registers pr ovide a method for sending data, commands, or command parameters or status to the pci interface. add-on write operatio ns to these registers may be in any width (byte, word, or dword). these registers may also be read. writing to one of thes e registers can optionally cause a pci bus interrupt (if desired) w hen the pci interrupt control/sta- tus register is properly configured. mailbox 4, byte 3 only exists as device pins on the s5335 device when used with a serial nonvolatile memory. this byte is not available if a byte-wide nv memory is used. add-on address offset: 10h, 14h, 18h, 1ch power-up value: xxxxxxxxh attribute: read/write size: 32 bits add-on fifo register port (afifo) register name: add-on fifo port this location provides access to the bidirectional fifo. separate registers are involved when reading and writing to this location. accordingly, it is not possible to read what was written to this location. the sequence of filling and emptying this fifo is established by the pci interface interrupt con- trol and status register. the fifo?s fullness may be observed by reading the master control/status register or agcsts register additionally, two signal pins are provided which reveal whether data is available (rdempty) or space to write into the fifo is available (wrfull). these signals may be used to interface with user supplied dma logic. caution must be exercised when using these flags for fifo transfers involv ing 64 bit endian conversion since the fifo must operate on dword pairs. add-on address offset: 20h power-up value: xxxxxxxxh attribute: read/write size: 32 bits s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 72 data sheet add-on controlled bus master write address register (mwar) this register is only accessible when add-on initiated bus mastering is enabled. this register is used to establish the pci address for data moving from the add-on bus to the pci bus dur- ing pci bus memory write operations. it consists of a 30-bit counter with the low-order two bits hardwired as zeros. transfers may be any non-zero byte length as defined by the transfer count register, mwtc and must begin on a dword boundary. this dword boundary starting constraint is placed upon this con- troller?s pci bus master tr ansfers so that byte lane alignment can be maintained between the s5335 con- troller?s internal fifo data path, the add-on interface, and the pci bus. note: applications which require a non-dword start- ing boundary will need to move the first few bytes under software program control (and without using the fifo) to establish a dword boundary. after the dword boundary is established the s5335 can begin the task of pci bus master data transfers. the master write address register is continually updated during the tr ansfer process a nd will always be pointing to the next unwritte n location. reading of this register during a transfer process (done when the s5335 controller is functioning as a target, i.e. not a bus master) is permitted and may be used to monitor the progress of the transfer . during the address phase for bus master write transfers, the two least significant bits presented on the pci bu s pins ad[31:0] will always be zero. this identifi es to the target memory that the burst address sequen ce will be in a linear order rather than in an intel 486 or pentium? cache line fill sequence. also, the pci bus address bit a1 will always be zero when this controller is the bus master. this signifies to the target that the s5335 controller is burst capable and that the ta rget should not arbitrarily disconnect after the first data phase of this operation. figure 32. add-on controlled bus master write address register register name: master write address add-on address offset: 24h power-up value: 00000000h attribute: read/write size: 32 bits 31 0 0 1 0 2bit value dword address (ro) write transfer address (r/w) s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 73 data sheet add-on pass-thru address register (apta) register name: add-on pass-thru address this register is employed when a response is desired when one of the base address decode regions is selected during an active pci bus cycle. when one of the base address decode registers 1-4 encounters a pci bus cycle which selects the region defined by it, this device latches that current cycle?s active address and asserts the signal ptatn# (pass-thru attention). wait states are generated on the pci bus until either data is transferred or the pci bus cycle is aborted by the initiator. this register provides a method for ?live? data (registered) transfers. intended uses include the emulating of other hard- ware as well as enabling the connection of existing external hardware to interface to the pci bus through the s5335. add-on address offset: 28h power-up value: xxxxxxxxh attribute: read only size: 32 bits add-on pass-thru data register (aptd) register name: add-on pass-thru data this register, along with apta de scribed above, is employed when a response is desired should one of the base address decode regions become selected during an active pci bus cycle. when one of the base address decode registers 1-4 encounters a pci bus cycle which selects the region defined by it, the apta register will contain that current cycle?s active address and the device asserts the signal ptatn# (pass-thru aten tion). wait states are generated on the pci bus until this register is read (pci bus writes) or this reg- ister is written (pci bus reads). add-on address offset: 2ch power-up value: xxxxxxxxh attribute: read/write size: 32 bits s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 74 data sheet add-on controlled bus master read address register (mrar) this register is only accessible when add-on initiated bus mastering is enabled. this register is used to establish the pci address for data moving to the add-on bus from the pci bus dur- ing pci bus memory read operations. it consists of a 30-bit counter with the low-order two bits hardwired as zeros. transfers may be any non-zero byte length as defined by the transfer count register, mrtc and must begin on a dword boundary. this dword bound- ary starting constraint is placed upon this controller?s pci bus master transfers so that byte lane alignment can be maintained between the s5335 controller?s internal fifo data path, the add-on interface and the pci bus. note: applications which require a non-dword start- ing boundary will need to move the first few bytes under software program control (and without using the fifo) to establish a dword boundary. after the dword boundary is established the s5335 can begin the task of pci bus master data transfers. the master read address register is continually updated during the tr ansfer process a nd will always be pointing to the next unread location. reading of this register during a transfer process (done when the s5335 controller is functioning as a target?i.e., not a bus master) is permitted and may be used to monitor the progress of the transfer . during the address phase for bus master read transfer s, the two least significant bits presented on the pci bus ad[31:0] will always be zero. this identifies to the target memory that the burst address sequence will be in a linear order rather than in an intel 486 or pentium? cache line fill sequence. also, the pci bus address bit a1 will always be zero when this controller is the bus master. this signifies to the target that the controlle r is burst capable and that the target should not arbi trarily disconnect after the first data phase of this operation. under certain circumstances, mrar can be accessed from the add-on bus instead of the pci bus. figure 33. add-on controlled bus master read address register register name: master read address add-on address offset: 30h power-up value: 00000000h attribute: read/write size: 32 bits 31 0 0 1 0 2bit value dword address (ro) read transfer address (r/w) s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 75 data sheet add-on empty/full status register (ambef) this register provides empty /full visibility of each byte within the mailboxes. the empty/full status for the out- going mailboxes are displayed on the high order 16 bits and the empty/full status for the incoming mail- boxes are presented on the low order 16 bits. a value of one signifies that a given mailbox had been written by the sourcing interface but had not yet been read by the corresponding destination interface. an incoming mailbox is defined as one in which data travels from the pci bus into the add-on bus and an outgoing mail- box is defined as one where data goes out from the add-on bus to the pci interface. figure 34. add-on mailbox empty/full status register register name: add-on mailbox empty/full status add-on address offset: 34h power-up value: 00000000h attribute: read only size: 32 bits 31 0 15 bit value incoming mailbox status (ro) outgoing mailbox status (ro) 16 s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 76 data sheet table 48. add-on mailbox empty/full status register bit description 31:16 outgoing mailbox status. this field indicates which out going mailbox registers have been written by the add-on bus interface but have not yet been read by the pci bus. each bi t location corresponds to a specific byte within one of the four outgoing mailboxes. a va lue of one for each bit signifies that the specified mailbox byte is full, a value of zero signifies empty. the mapping of these status bi ts to bytes within each mailbox is as follows: bit 31 = outgoing mailbox 4 byte 3 bit 30 = outgoing mailbox 4 byte 2 bit 29 = outgoing mailbox 4 byte 1 bit 28 = outgoing mailbox 4 byte 0 bit 27 = outgoing mailbox 3 byte 3 bit 26 = outgoing mailbox 3 byte 2 bit 25 = outgoing mailbox 3 byte 1 bit 24 = outgoing mailbox 3 byte 0 bit 23 = outgoing mailbox 2 byte 3 bit 22 = outgoing mailbox 2 byte 2 bit 21 = outgoing mailbox 2 byte 1 bit 20 = outgoing mailbox 2 byte 0 bit 19 = outgoing mailbox 1 byte 3 bit 18 = outgoing mailbox 1 byte 2 bit 17 = outgoing mailbox 1 byte 1 bit 16 = outgoing mailbox 1 byte 0 15:00 incoming mailbox status. this field indicates which inco ming mailbox registers have been written by the pci bus but not yet been read by the add-on interface. each bit locati on corresponds to a specific byte within one of the four incoming mailboxes. a value of one for each bit signifies that the specified mailbox byte is full, a value of zero signi- fies empty. the mapping of these status bits to bytes within each mailbox is as follows: bit 15 = incoming mailbox 4 byte 3 bit 14 = incoming mailbox 4 byte 2 bit 13 = incoming mailbox 4 byte 1 bit 12 = incoming mailbox 4 byte 0 bit 11 = incoming mailbox 3 byte 3 bit 10 = incoming mailbox 3 byte 2 bit 9 = incoming mailbox 3 byte 1 bit 8 = incoming mailbox 3 byte 0 bit 7 = incoming mailbox 2 byte 3 bit 6 = incoming mailbox 2 byte 2 bit 5 = incoming mailbox 2 byte 1 bit 4 = incoming mailbox 2 byte 0 bit 3 = incoming mailbox 1 byte 3 bit 2 = incoming mailbox 1 byte 2 bit 1 = incoming mailbox 1 byte 1 bit 0 = incoming mailbox 1 byte 0 s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 77 data sheet add-on interrupt control/status register (aint) this register provides the method for choosing which conditions are to produce an interrupt on the add-on bus interface, a method for viewing the cause for the interrupt, and a method for acknowledging (removing) the interrupt?s assertion. interrupt sources: ? one of the incoming mailboxes (1,2,3 or 4) becomes full. ? one of the outgoing mailboxes (1,2,3 or 4) becomes empty. ? built-in self test issued. ? write transfer count = zero ? read transfer count = zero ? target/master abort figure 35. add-on interrup t control/status register register name: add-on interrupt control and status add-on address offset: 38h power-up value: 00000000h attribute: read/write, read/ write_one_clear size: 32 bits 31 24 23 201918 21 17 12 8 4 0 bit value d4-d0 incoming mailbox (becomes full) d4=enable interrrupt d3-d2=mailbox # 0 0=mailbox 1 0 1=mailbox 2 1 0=mailbox 3 1 1=mailbox 4 d0-d1=byte # 0 0=byte 0 0 1=byte 1 1 0=byte 2 1 1=byte 3 d12-d8 outgoing mailbox (r/w) (goes empty) d12=enable interrupt d11-d10=mailbox 0 0=mailbox 1 0 1=mailbox 2 1 0=mailbox 3 1 1=mailbox 4 d9-d8=byte # 0 0=byte 0 0 1=byte 1 1 0=byte 2 1 1=byte 3 16 1514 0 0 0 0 0 0 0 0 0 0 interrupt asserted (ro) bus mastering error interrupt (r/wc) bist (r/wc) read transfer complete (r/wc) write transfer complete (r/wc) interrupt on read transfer complete outgoing mailbox interrupt (r/wc) incoming mailbox interrupt (r/wc) 0 0 0 interrupt source (r/w) enable & selection interrupt on write transfer complete interrupt status interrupt selection s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 78 data sheet table 49. interrupt control/status register bit description 31:24 reserved. always zero. 23 interrupt asserted. this read-only status bit indicates that one or more interrupt conditions is present. this bit is nothing more than the oring of the interrupt conditions described by bits , 20, 17 and 16 of this register. 22 reserved. always zero. 21 master/target abort. this bit signifies that an interrupt has been generated due to the s5335 encountering a master or target abort during an s5335 initiated pci bus cycle. this bit operates as read or write one clear. writing a one to this bit causes it to be cleared. writing a zero to this bit does nothing. 20 bist. built-in self-test interrupt. this interrupt occurs when a self test is initiated by the pci interface writing of the bist configuration register. this bit will stay set until clear ed by writing a one to this location. self test completion codes may be passed to the pci bist register by writing to the agcsts register. 19 read transfer complete. this bit signifies that an interru pt has been generated due to the completion of a pci bus master operation involving the transfer of data from the pci bus to the add-on. this interrupt will occur when the master read transfer count register reaches zero. this bit operates as read or write one clear. a write to this bit with the data of one will cause this bit to be reset; a write to this bit with the data of zero will not change the state of this bit. 18 write transfer complete. this bit signifies that an inte rrupt has been generated due to the completion of a pci bus master operation involving the transfer of data to the pc i bus from the add-on. this interrupt will occur when the master write transfer count register reaches zero. this bit operates as read or write one clear. a write to this bit with the data of one will cause this bit to be reset; a write to this bit with the data of zero will not change the state of this bit. 17 outgoing mailbox interrupt. this bit sets when the mailbox se lected by bits 12 through 8 of this register is read by the pci interface. this bit operates as read or write one cl ear. a write to this bit with the data as one will cause this bit to be reset; a write to this bit with the dat a as zero will not change the state of this bit. 16 incoming mailbox interrupt. this bit sets when the mailbox selected by bits 4 through 0 of this register are written by the pci interface. this bit operates as read or write one cl ear. a write to this bit with the data of one will cause this bit to be reset; a write to this bit with the dat a as zero will not change the state of this bit. 15 interrupt on read transfer complete. this bit enables the occurrence of an interrupt w hen the read transfer count reaches zero. this bit is read/write. 14 interrupt on write transfer complete. this bit enables t he occurrence of an interrupt when the write transfer count reaches zero. this bit is read/write. 13 reserved. always zero. 12 enable outgoing mailbox interrupt. this bit allows a read by the pci of the outgoing ma ilbox register identified by bits 11 through 8 to produce an add-on interface interrupt. this bit is read/write. 11:10 outgoing mailbox interrupt select. this field selects which of the four outgoing mailboxes is to be the source for causing an outgoing mailbox interrupt. [00]b selects mailbox 1, [01]b selects mailbox 2, [10]b selects mailbox 3 and [11]b selects mailbox 4. this field is read/write. 9:8 outgoing mailbox byte interrupt select. this field select s which byte of the mailbox selected by bits 11 and 10 above is to actually cause the interrupt. [00] b selects byte 0, [01]b selects byte 1, [10]b selects byte 2, and [11]b selects byte 3. this fiel d is read/write. 7:5 reserved. always zero. 4 enable incoming mailbox interrupt. this bit allows a write from the pci bus to the incoming mailbox register identi- fied by bits 3 through 0 to produce an add-on interface interrupt. this bit is read/write. s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 79 data sheet 3:2 incoming mailbox interrupt select. this field selects which of the four incoming mailboxes is to be the source for causing an incoming mailbox interrupt. [00]b selects mailbox 1, [01]b selects mailbox 2, [10]b selects mailbox 3 and [11]b selects mailbox 4. this field is read/write. 1:0 incoming mailbox byte interrupt select. this field selects which byte of the mailbox sele cted by bits 3 and 2 above is to actually cause the interrupt. [00]b selects byte 0, [01]b selects byte 2, and so on. table 49. interrupt control/status register (continued) bit description s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 80 data sheet add-on general control/status register (agcsts) this register provides for ov erall control of the add-on portion of this device. it is used to provide a method to perform software resets of the mailbox and fifo flags. the following add-on controls are provided: ? reset pci to add-on fifo flags ? reset add-on to pci fifo flags ? reset mailbox empty full status flags ? write/read external non-volatile memory. the following status flags are provided to the add-on: ? add-on to pci fifo full ? add-on to pci fifo has four or more empty locations ? add-on to pci fifo empty ? pci to add-on fifo full ? pci to add-on fifo has four or more words loaded ? pci to add-on fifo empty figure 36. add-on genera l control/status register register name: add-on general control and status add-on address offset: 3ch power-up value: 000000f4h (pci initiated bus mastering) 00000034h (add- on initiated bus mastering) attribute: read/write, read only, write only size: 32 bits 31 292827 2524 23 0 12 11 765 bit value fifo status (ro) d5=pci to add-on fifo empty d4=pci to add-on 4+ spaces d3=pci to add-on fifo full d2=add-on to pci fifo empty d1=add-on to pci fifo 4+ words d0=add-on to pci fifo full 16 15 0 0 bist condition code (r/w) reset controls d27=mailbox flags d26=pci to add-on fifo status flags d25=add-on to pci fifo status flags nv operation address/data nvram access ctrl transfer count enable d6=read transfer count equals zero (ro) d7=write transfer count equals zero (ro) s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 81 data sheet table 50. add-on general control/status register bit description 31:29 nvram/eprom access control. this field provides a me thod for access to the optional, external non-volatile mem- ory. write operations are achieved by a sequence of byte opera tions involving these bits and the 8-bit field of bits 23 through 16. the sequence requir es that the low-order address, high-order address, and then a data byte be loaded in order. bit 31 of this field acts as an enable/clock and ready for the access to the external memory. d31 must be written to a 1 before an access can begin, and subsequent accesses must wait for bit d31 to become zero (ready). d31 d30 d29 w/r 0 x x w inactive 1 0 0 w load low address byte 1 0 1 w load high address byte 1 1 0 w begin write 1 1 1 w begin read 0 x x r ready 1 x x r busy cautionary note: the non-volatile memo ry interface is also available for a ccess by the pci bus interface. accesses by both the add-on and pci bus to the nv memory are not directly supported by this component. software must be designed to prevent the simultaneous access of nv memo ry to prevent data corruptio n within the memory and pro- vide for accurate data retrieval. 28 transfer count enable. when set, transfer counts are used for add-on initiated bus master transfers. when clear, transfer counts are ignored. 27 mailbox flag reset. writing a 1 to this bit causes all mailbox status flags to become reset (empty). it is not neces- sary to write this bit as 0 because it is used internally to produce a reset pulse. since reading of this bit will always produce zeros, this bit is write only. 26 add-on to pci fifo status reset. writing a one to this bit causes the outbound (bus master writes) fifo empty flag to set indicating empty and the fifo full flag to re set and the fifo four plus words available flag to reset. it is not necessary to write this bit as zero because it is us ed internally to produce a reset pulse. since reading of this bit would always produce zeros, this bit is write only. 25 pci to add-on fifo status reset. writing a 1 to this bi t causes the inbound (bus master reads) fifo empty flag to set indicating empty and the fifo full flag to reset and the fi fo four plus spaces flag to set. it is not necessary to write this bit as 0 because it is used internally to pr oduce a reset pulse. since reading of this bit would always pro- duce zeros, this bit is write only. 24 reserved. always zero. 23:16 non-volatile memory address/data port. this 8-bit field is us ed in conjunction with bit 31, 30 and 29 of this register to access the external non-volatile memory. the contents wr itten are either low address, high address, or data as defined by bits 30 and 29. this register will contain the external non-volatile memory data when the proper read sequence for bits 31 through 29 is performed. 15:12 bist condition code. this field is di rectly connected to the pci configuration self test register. bit 15 through 12 maps with the bist register bits 3 through 0, respectively. 11:8 reserved. always zero. 7 add-on to pci transfer count equal zero (ro). this bit as a one signifies that the write transfer count is all zeros. only when add-on initiated bus mastering is enabled. s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 82 data sheet 6 pci to add-on transfer count equals zero (ro). this bit as a one signifies that the read transfer count is all zeros. only when add-on initiated bus mastering is enabled. 5 pci to add-on fifo empty. this bit is a 1 when the pci to add-on fifo is empty. 4 pci to add-on fifo 4+ spaces. this bit is a 1 when there are four or more open spaces in the pci to add-on fifo. 3 pci to add-on fifo full. this bit is a 1 when the pci to add-on fifo is full. 2 add-on to pci fifo empty. this bit is a 1 when the add-on to pci fifo is empty. 1 add-on pci fifo 4+ words. this bit is a 1 when there ar e four or more full locations in the add-on to pci fifo. 0 add-on to pci fifo full. this bit is a 1 when the add-on to pci fifo is full. table 50. add-on general contro l/status register (continued) bit description s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 83 data sheet add-on controlled bus master write transfer count register (mwtc) this register is only acce ssible when add-on initiated bus mastering is enabled. the master write transfer count register is used to con- vey to the s5335 controller the actual number of bytes that are to be transferred. the value in this register is decremented with each bus master pci write opera- tion until the transfer count reaches zero. upon reaching zero, the transfer operation ceases and an interrupt may be optionally generated to either the pci or add-on bus interface. transfers which are not whole multiples of dwords in size result in a partial word ending cycle. this partial word ending cycle is possible since all bus master transfers for this control- ler are required to begin on a dword boundary. figure 37. add-on controlled bus master write transfer count register register name: master write transfer count add-on address offset: 58h power-up value: 00000000h attribute: read/write size: 32 bits 31 0 25 bit value transfer count in bytes (r/w) reserved = o's (ro) 26 00 s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 84 data sheet add-on controlled bus master read transfer count register (mrtc) this register is only acce ssible when add-on initiated bus mastering is enabled. the master read transfer count register is used to con- vey to the pci controller the actual number of bytes that are to be transferred. the value in this register is decremented with each bus master pci read opera- tion until the transfer count reaches zero. upon reaching zero, the transfer operation ceases and an interrupt may be optionally generated to either the pci or add-on bus interface. transfers which are not whole multiples of dwords in size result in a partial word ending cycle. this partial word ending cycle is possible since all bus master transfers for this control- ler are required to begin on a dword boundary. figure 38. add-on controlled bus master read transfer count register register name: master read transfer count add-on address offset: 5ch power-up value: 00000000h attribute: read/write size: 32 bits 31 0 25 bit value transfer count in bytes (r/w) reserved = 0's (ro) 26 00 s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 85 data sheet initialization all pci bus agents and bridges are required to imple- ment pci configuration regi sters. when multiple pci devices are present, these re gisters must be unique to each device in the system. the specified pci proce- dure for uniquely selecting a device?s configuration space involves a dedicated signal, called idsel, con- nected to each motherboard pci bus device and pci slot. the host executes configurat ion cycles after reset to each device on the pci bus. the configuration regis- ters provide information on pci agent operation and memory or i/o space requirements. these allow the pci bios to enable the device and locate it within sys- tem memory or i/o space. after a pci reset, the s5335 can be configured for a specific application by down loading device setup infor- mation from an external non-volatile memory into the device configuration registers. the s5335 can also be used in a default configuration, with no external boot device. when using a non-volatile boot memory to customize operation, 64 bytes are required for s5335 setup infor- mation. the rest of the boot device may be used to implement an expansion bios, if desired. some of the setup information is used to initialize the s5335 pci configuration registers, other information is not down- loaded into registers, but is used to define s5335 operation (fifo interface, pass-thru operation, etc.). pci reset immediately following the assertion of the pci rst# signal, the add-on reset output sysrst# is asserted. immediately following the deassertion of rst#, sysrst# is deasserted. the add-on reset output may be used to initialize st ate machines, reset add-on microprocessors, or reset other add-on logic devices. all s5335 operation registers and configuration reg- isters are initialized to their default states at reset. the default values for the configuration registers may be overwritten with the contents of an external nv boot memory during device initiali zation, allowing a custom device configuration. conf iguration accesses by the host cpu to the s5335 produce pci bus wait states until one of the following events occurs: ? the s5335 identifies that there is no valid boot memory (and default configuration register values are used). ? the s5335 finishes downloading all configura- tion information from a valid boot memory. loading from by te-wide nv memo - ries the snv input on the s5335 indicates what type of external boot-load device is present (if any). if snv is tied low, a byte-wide nv memory is assumed. in this case, immediately after the pci bus reset is deas- serted, the address 0040h is presented on the nv memory interface address bus ea[15:0]. eight pci clocks later (240 ns at 33 mhz), data is read from the nv memory data bus eq[7:0] and address 0041h is presented. after an additiona l eight pci clocks, data is again read from eq7:0. if both accesses read are all ones (ffh), it implies an illegal vendor id value, and the external nv memory is not valid or not present. in this situation, the amcc default configuration values are used. if either of the accesses to address 0040h and 0041h contain zeros (not ffh), the next accesses are to loca- tions 0050h, 0051h, 0052h, and 0053h. at these locations, the data must be c0h (or c1h or c2h), ffh, e8h, and 10h, respectively, for the external nv memory to be valid. once a valid external nv memory has been recognized, it is read, sequentially, from location 0040h to 007fh. the appropriate data is loaded into the pci configuration registers as described in chap- ter 4. some of the boot device data is not downloaded into configuration registers, but is used to enable fea- tures and configure s5335 operation. upon completion of this procedur e, the boot-load sequence terminates and pci configur ation accesses to the s5335 are acknowledged with the pci target ready (trdy#) output. table 51 lists the required nv memory contents for a valid configuration nv memory device. s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 86 data sheet loading from serial nv memories snv tied high indicates that a serial nv memory (or no external device) is present. when serial nv memories are used, data transfer is performed through a two- wire, bidirectional data transf er protocol as defined by commercial serial eeprom/flash offerings. these devices have the advantages of low pin counts, small package size, and economical price. a serial nv memory is consider ed valid if the first serial accesses contain the correct per-byte acknowledg- ments (see figure 41). if the serial per-byte acknowledgment is not observed, the s5335 deter- mines that no external serial nv memory is present and the amcc default configuration register values are used. two pins are used to transf er data between the s5335 pci controller and the external serial memory: a serial clock pin, scl, and a serial data pin, sda. the serial clock pin is an output from the s5335, and the serial data pin is bidirectional. the serial clock is derived by dividing the pci bus clock by 512. this means that the frequency of the serial clock is approximately 65 khz for a 33-mhz pci bus clock. note: when a serial boot dev ice is used, ea9 is de- fined as a scl divide by control pin. if ea9 = 1 then scl = pclk/512 if ea9 = 0 then scl = pclk/8 this pin should be pulled high. communications with the serial memory involve sev- eral clock transitions. a start event signals the beginning of a transaction and is immediately followed by an address transfer. each address/data transfer consists of 8 bits of info rmation followed by a 1-bit acknowledgment. when the exchange is complete, a stop event is issued. figure 39 shows the unique rela- tionship defining both a start and stop event. figure 40 shows the required timing for address/data with respect to the serial clock. for random accesses, the sequence involves one clock to define the start of the sequence, eight clocks to send the slave address and read/write command, followed by a one-clock acknowledge, and so on. fig- ure 41 shows the sequence for a random write access requiring 29 serial clock transitions. at the clock speed for the s5335, this corresponds to one byte of data transferred approximately every 0.5 milliseconds. read accesses may be either random or sequential. random read access requires a dummy write to load the word address and require 39 serial clock transi- tions. figure 42 shows the sequence for a random byte read. to initialize the s5335 controller?s pci configuration registers, the smallest seri al device necessary is a 128 x 8 organization. although the s5335 controller only requires 64 bytes, these bytes must begin at a 64- byte address offset (0040h through 007fh). this offset constraint permits the configuration image to be shared with a memory containing expansion bios code and the necessary preamble to identify an expansion bios. the largest serial device which may be used is 2 kbytes. table 51. valid external boot memory contents address data notes 0040h-41h not ffffh this is the location that the s5335 pci controller will load a customized vendor id. (ffffh is an illegal vendor id.) 0050h c2h, c1h or c0h this is the least si gnificant byte of the region which init ializes the base address register #0 of the s5335 configuration regi ster (section 3.11). a valu e of c1h assigns the 16 dword locations of the pci operation registers into i/o space, a value of c0h defines memory space, a value of c2h defines memory space below 1 mbyte. 0051 ffh required. 0052h e8h required. 0053h 10h required. s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 87 data sheet figure 39. serial interface definition of start and stop figure 40. serial interf ace clock/data relationship figure 41. serial interf ace byte access ? write figure 42. serial inte rface byte access ? read scl sda start bit stop bit dat a stable dat a stable dat a change scl sda slave address dat a 1 0 1 0 word address * s t a r t a c k a c k a c k r/w 0 s t o p slave address 1 0 1 0 word address s t a r t a c k a c k r/w 0 data * a c k 1 slave address 1 0 1 0 s t a r t a c k r/w s t o p s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 88 data sheet pci bus configuration cycles cycles beginning with the assertion idsel and frame# along with the two configuration command states for c/be[3:0] (configuration read or write) access an individual devic e?s configuration space. during the address phase of the configuration cycle just described, the values of ad0 and ad1 identify if the access is a type 0 configuration cycle or a type 1 configuration cycle. type 0 cycles have ad0 and ad1 equal to 0 and are used to access pci bus agents. type 1 configuration cycles are intended only for bridge devices and have ad0 as a 1 with ad1 as a 0 during the address phase. the s5335 pci device is a bus agent (not a bridge) and responds only to a type 0 configuration accesses. figure 43 depicts the state of the ad bus during the address phase of a type 0 configuration access. the s5335 controller does not support the multiple function numbers field (ad[10:8]) and only responds to the all- zero function number value. the configuration registers for the s5335 pci control- ler can only be accessed under the following conditions: ? idsel high (pci slot unique signal which iden- tifies access to configuration registers) along with frame# low. ? address bits a0 and a1 are 0 (identifies a type 0 configuration access). ? address bits a31-a11 are ignored. ? address bits a8, a9, and a10 are 0 (function number field of zero supported). ? command bits, c/be[3:0]# must identify a con- figuration cycle command (101x). figure 44 describes the signal timing relationships for configuration read cycles. figure 45 describes config- uration write cycles. figure 43. pci ad bus definition during a type 0 configuration access function number reserved register number 0 31 11 10 8 7 2 1 0 type 0 00xxxxxx - internal register address (device id, etc.) only 000 value supported by this device. 0 s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 89 data sheet figure 44. type 0 configuration read cycles figure 45. type 0 configuration write cycles pci clock frame # ad [31:0] c/be [3:0]# irdy# trdy# idsel devsel# address (i) (i) (i) (i) (t) (i) (t) (t) data byte enables config. read cmd 1 2 3 4 note select condition if frame # still asserted during clock 2, controller asserts stop# during 3 driven by controller during clock 3 driven by controller during clocks 2,3 +4 driven by controller during clocks 2,3 +4 (i) = driven by initiator (t) = driven by target pci clock frame # ad [31:0] c/be [3:0]# irdy# trdy# idsel devsel# address data byte enables config write cmd 1 2 3 4 note select condition frame # deasserted in clock 2, signifies only one data phase driven by controller during clocks 2+3 driven by controller during clocks 2+3 (t) (i) (t) (i) (i) (i) (i) (i) = driven by initiator (t) = driven by target s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 90 data sheet expansion bios roms this section provides an ex ample of a typical pc-com- patible expansion bios ro m. address offsets 0040h through 007fh represent the portion of the external nv memory used to boot-load the s5335 controller. whether the expansion rom is intended to be execut- able code is determined by the contents of the first three locations (starting at offset 0h) and a byte check- sum over the defined length. the defined length is specified in the byte at address offset 0002h. table 52 lists each field location by its address offset, its length, its value, and description. table 52. pc compatible expansion rom byte offset byte length binary value description example 0h 1h 2h 3h 7h-17h 18h-19h 20h-3fh 1 1 1 4 17h 2 32h 55h aah var. var. var. var. var bios rom signature byte 1 bios rom signature byte 2 length in multiples of 512 bytes entry point for init function. reserved (application unique data) pointer to pci data structure (see table 53) user-defined 55h aah 01h the following represents the boot-load image for t he s5335 controller?s pci configuration register: 40h 42h 44h 45h 46h 48h 49h 4ch 4dh 4eh 4fh 50h 51h 52h 53h 54h 58h 5ch 60h 64h 2 2 1 1 2 1 3 1 1 1 1 1 1 1 1 4 4 4 4 4 [your vendor id] [your device id] not used [bus master config.] not used [your revision id] [your class code] not used [your latency timer #] [your header type] [self-test if desired] c0h, c1h or c2h ffh e8h 10h [base addr. #1] [base addr. #2] [base addr. #3] [base addr. #4] [base addr. #5] 10e8h 4750h 00h 80h ff0000h 00h 00h 80h or 00h c0h, c1h or c2h ffh e8h 10h xxxxxxxxh xxxxxxxxh xxxxxxxxh xxxxxxxxh xxxxxxxxh s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 91 data sheet a 16-bit pointer at location 18h of the pc expansion rom identifies the start offset of the pci data struc- ture. the pci data structure is shown in table 53 and contains various vendor, product, and program evolu- tions. if a valid external nv memory is identified by the s5335, the pci data structure is used to configure the s5335. the pci data structure is not necessary for this device to operate. if no external nv memory is imple- mented, the s5335 boots with the default configuration values. note: if a serial bios rom is used, the access time for large serial devices should be considered, since it may cause a lengthy system delay during initialization. for example, a 2-kbyte serial device takes about 1 second to be read. many systems, even when bios roms are ultimately shadowed into system ram, may read this memory space twice (once to validate its size and checksum, and once to move it into ram). execu- tion directly from a serial bios rom, although possible, may be unacceptably slow. 68h 70h 74h 7ch 7dh 7eh 7fh 8 4 8 1 1 1 1 not used [expansion rom base addr.] not used [interrupt line] [interrupt pin] [min-grant] [max_lat] (example shows 32k bytes) ffff8001h 0ch 01h 00h 00h 80h ? (1ffh), or (2ffh), or (3ffh), etc. application specific byte checksum, location dependent on value for length field at offset 0002h. table 52. pc compatible expansion rom (continued) byte offset byte length binary value description example table 53. pci data structure byte offset byte length binary value description 0h 4h 6h 8h ah ch dh 10h 12h 14h 15h 16h 4 2 2 2 2 1 3 2 2 1 1 2 ?pcir? var. var. var. var. var. var. var. var. var. var. 0000h signature, the ascii string ?pcir? where ?p? is at offset 0, ?c? at offset 1, and so on. vendor identification device identification pointer to vital product data pci data structure length (starts with signature field) pci data structure revision (=0 for this definition) class code image length revision level code type indicator (bit d7=1 signifies ?last image?) reserved s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 92 data sheet pci bus interface this section describes the various events which occur on the s5335 pci bus interface. since the s5335 con- troller functions as both a target (slave) and an initiator (master), signal timing detail is given for both situa- tions this section presents the signal relationships involved in performing basic read or write transfers on the pci bus and also describes the different ways these cycles may complete. pci bus transactions because the pci bus has multiplexed address/data pins, ad[31:0], each pci bus transaction consists of two phases: address and da ta. an address phase is defined by the clock peri od when the signal frame# transitions from inactive (hi gh) to active (low). during the address phase, a bus command is also driven by the initiator on signal pins c/be[3:0]#. if the command indicates a pci read, the clock cycle following the address phase is used to perform a ?bus turn-around? cycle. a turn-around cycle is a clock period in which the ad bus is not driven by the initiator or the target device. this is used to avoid pci bus contention. for a write command, a turn-aro und cycle is not needed, and the bus goes directly from the address phase to the data phase. all pci bus transactions c onsist of an address phase (described above), followed by one or more data phases. the address phase is only one pci clock long and the bus cycle information (address and command) is latched internally by the s5335. the number of data phases depends on how many data transfers are desired or are possible with a given initiator-target pair. a data phase consists of at least one pci clock. frame# is deasserted to indicate that the final data phase of a pci cycle is occurring. wait states may be added to any data phase (each wait state is one pci clock). the pci bus command presented on the c/be[3:0]# pins during the address phase can represent 16 possi- ble states. table 54 lists the pci commands and identifies those which are supported by the s5335 controller as a target and those which may be pro- duced by the s5335 controller as an initiator. a ?yes? in the ?supported as target? column in table 54 indi- cates the s5335 controller asserts the signal devsel# when that command is issued along with the appropriate pci address. two commands are sup- ported by the s5335 controlle r as an initiator: memory read and memory write. the completion or termination of a pci cycle can be signaled in several ways. in most cases, the comple- tion of the final data phase is indicated by the assertion of ready signals from both the target (trdy#) and initiator (irdy#) while frame# is inac- tive. in some cases, the target is not be able to continue or support a burst transfer and asserts the stop# signal. this is referred to as a target discon- nect. there are also cases where an addressed device does not exist, and t he signal devsel# never becomes active. when no devsel# is asserted in response to a pci cycle, the initiator is responsible for ending the cycle. this is referred to as a master abort. the bus is returned to the idle phase when both frame# and irdy# are deasserted. s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 93 data sheet 1. memory read multiple and read line are treated as memory reads. 2. memory write & invalidate commands are treated as memory writes. 3. must be enabled by bit 15 mcsr. table 54. supported pci bus commands c/be[3:0]# command type supported as target supported as initiator 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 interrupt acknowledge special cycle i/o read i/o write reserved reserved memory read memory write reserved reserved configuration read configuration write memory read multiple reserved memory read line memory write & invalidate no no yes yes no no yes yes no no yes yes yes 1 no yes 1 yes 2 no no no no no no yes yes no no no no no 3 no no no s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 94 data sheet pci burst transfers the pci bus, by default, expects burst transfers to be executed. to successfully perform a burst transfer, both the initiator and target must order their burst address sequence in an identical fashion. there are two different ordering schemes: linear address incre- menting and 80486 cache line fill sequencing. the exact ordering scheme for a bus transaction is defined by the state of the two least significant ad lines during the address phase. the decoding for these lines is shown below: the s5335 supports both the linear and the cache line burst ordering. when the s5335 controller is an initia- tor, it always employs a linear ordering. some accesses to the s5335 controller (as a target) can not be burst transfers. for example, the s5335 does not allow burst transfers when accesses are made to the configuration or operation registers (including the fifo as a target). attempts to perform burst transfers to these regions cause stop# to be asserted during the first data phase. the s5335 com- pletes the initial data phase successfully, but asserting stop# indicates that the next access needs to be a completely new cycle. accesses to memory or i/o regions defined by the base address registers 1-4 may be bursts, if desired. pci read transfers the s5335 responds to pci bus memory or i/o read transfers when it is selected (target). as a pci bus ini- tiator, the s5335 controller may also produce pci bus memory read operations. figure 46 depicts the fastest burst read transfer possi- ble for the pci bus. the timings shown in figure 46 are representative of the s5335 as a pci initiator with a fast, zero-wait-state memory target. the signals driven by the s5335 during the transfer are frame#, c/be[3:0]#, and irdy#. the signals driven by the tar- get are devsel# and trdy#. ad[31:0] are driven by both the target and initiator during read transactions (only one during any given cl ock). clock period 2 is a required bus turn-around clock which ensures bus contention between the initiator and target does not occur. targets drive devsel# and trdy# after the end of the address phase (boundary of clock periods 1 and 2 of figure 46). trdy# is not driven until the target can provide valid data for the pci read. when the s5335 becomes the pci initiator, it attempts to perform sus- tained zero-wait state burst reads until one of the following occurs: ? the memory target aborts the transfer ? pci bus grant (gnt#) is removed ? the pci to add-on fifo becomes full ? a higher priority (add-on to pci) s5335 trans- fer is pending (if programmed for priority) ? the read transfer byte count reaches zero ? bus mastering is disabled from the add-on interface figure 46. zero wait state burst read pci bus transfer (s5335 as initiator) ad[1:0] burst order 0 0 linear sequence 0 1 reserved 1 0 cacheline wrap mode 1 1 reserved 1 2 3 4 5 pci clock frame # ad [31:0] c/be [3:0]# irdy# trdy# devsel# address data (2) data (3) (t) (t) (t) data (1) byte en (2) byte en (3) (i) = driven by initiator (t) = driven by target byte enables (1) bus command (i) (t) (i) (i) (i) (t) 6 s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 95 data sheet read accesses from the s5335 operation registers (s5335 as a target) are shown in figure 47. the s5335 conditionally asserts stop# in clock period 3 if the initiator keeps frame# asserted during clock period 2 with irdy# asserted (indicating a burst is being attempted). wait states may be added by the ini- tiator by not asserting the signal irdy# during clock 3 and beyond. if frame# remains asserted, but irdy# is not asserted, the initiato r is just adding wait states, not necessarily attempting a burst. there is only one condition where accesses to s5335 operation registers do not re turn trdy# but do assert stop#. this is called a target-initiated termination or target disconnect and occurs when a read attempt is made to an empty s5335 fifo. the assertion of stop# without the assertion of trdy# indicates that the initiator should retry the operation later. when burst read transfers are attempted to the s5335 operation registers, stop# is asserted during the first data transfer to indicate to the initiator that no further transfers (data phases) are pos sible. this is a target- initiated termination where the target disconnects after the first data transfer. figu re 48 shows the signal rela- tionships during a burst read attempt to the s5335 operation registers. figure 47. single data phase pci bus read of s5335 registers (s5335 as target) figure 48. burst pci bus read attempt to s5335 registers (s5335 as target) frame # ad[31:0] c/be[3:0]# irdy# trdy# devsel# stop# address dat a byte enables bus command 1 23 4 5 (i) (i) (i) (t) (t) (t) (i) (t) (i) = driven by initiator (t) = driven by target pci clock frame # ad[31:0] c/be[3:0]# irdy# trdy# devsel# stop# address data byte enables (1) 1 23 4 5 (i) (i) (t ) (t ) (t ) (t) (i) (i) be (2) bus command (i) = driven by initiator (t) = driven by target s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 96 data sheet pci write transfers write transfers on the pci bus are one clock period shorter than read transfers . this is because the ad[31:0] bus does not re quire a turn -around cycle between the address and data phases. when the s5335 is accessed (target) , it responds to a pci bus memory or i/o transfers. as a pci initiator, the s5335 controller can also execute pci memory write operations. the timing diagram in figure 49 represents an s5335 initiator pci write operation tr ansferring to a fast, zero- wait-state memory target. the signals driven by the s5335 during the transfer are frame#, ad[31:0], c/ be[3:0]#, and irdy#. the signa ls driven by the target are devsel# and trdy#. as with pci reads, targets assert devsel# and trdy# af ter the clock defining the end of the address phas e (boundary of clock peri- ods 1 and 2 of figure 49). trdy# is not driven until the target has accepted the data for the pci write. when the s5335 becomes the pci initiator, it attempts sustained zero-wait state burst writes until one of the following occurs: ? the memory target aborts the transfer ? pci bus grant (gnt# is removed) ? the add-on to pci fifo becomes empty ? a higher priority (pci to add-on) s5335 trans- fer is pending (if programmed for priority) ? the write transfer by te count reaches zero ? bus mastering is disabled from the add-on interface write accesses to the s5335 operation registers (s5335 as a target) are shown in figure 50. here, the s5335 asserts the signal stop# in clock period 3. stop# is asserted because the s5335 supports fast, zero-wait-state write cycles but does not support burst writes to operation registers. wait states may be added by the initiator by not asserting the signal irdy# during clock 2 and beyond. there is only one condition where writes to s5335 operation registers do not return trdy# (but do assert stop#). this is called a target-initiated term ination or target discon- nect and occurs when a write attempt is made to a full s5335 fifo. as with the read transfers, the assertion of stop# without the assertion of trdy# indicates the initiator should retry the operation later. figure 49. zero wait state burst writ e pci bus transfer (s5335 as initiator) pci clock frame # ad [31:0] c/be [3:0]# irdy# trdy# devsel# address data 1 byte en 1 1 234 (i) (i) (t) (t) (i) (i) byte en 3 byte en 2 data 2 data 3 * bus command = memory write data transfer #1 data transfer #2 data transfer #3 6 bus command* (i) = driven by initiator (t) = driven by target 5 s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 97 data sheet master-initiated termination occasionally, a pci transfer must be terminated by the initiator. typically, the initiator terminates a transfer upon the successful completion of the transfer. some- times, the initiator?s bus mastership is relinquished by the bus arbiter (gnt# is removed), often because another device requires bus ownership. this is called initiator preemption and is di scussed in la ter sections. when the s5335 is an initiator and does not observe a devsel# response to its assertion of frame#, it ter- minates the cycle (master abort). normal cycle completion a successful data transfer occurs when both the initia- tor and target assert their respective ready signals, irdy# and trdy#. the last data phase is indicated by the initiator when frame# is deasserted during a data transfer. a normal cycl e completion occurred if the target does not assert stop#. figure 51 shows the signal relationships defining a normal transfer completion. figure 50. single data phase pci bus wr ite of s5335 registers (s5335 as target) figure 51. master-initiated, normal completion (s5335 as either target or initiator) pci clock frame # ad[31:0] c/be[3:0]# irdy# trdy# devsel# stop# address data 1 byte en 1 bus command 1 2 3 4 5 (i) (i) (t) (t) (i) (i) byte en 2 data 2 data transfer #1 no data transferred 6 (t) if burst attempt (i) = driven by initiator (t) = driven by target pci clock frame # irdy# trdy# devsel# 1 2 3 (t) (t) (i) (t) normal completion (i) (i) = driven by initiator (t) = driven by target stop# s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 98 data sheet initiator preemption a pci initiator (bus master) is said to be preempted when the system platform deas serts the initiator?s bus grant signal, gnt#, while it still requests the bus (req# asserted). this situatio n occurs if the initiator?s latency timer expires and the system platform (bus arbitrator) has a bus master request from another device. the s5335 master la tency timer register con- trols the s5335 responsivenes s to the removal of a bus grant (preemption). the presence of a master latency timer register c an cause two preemption situations: 1. removal of gnt# when the latency timer is non- zero (s5335 is guaranteed to still ?own the bus?). 2. removal of the gnt# after the latency timer has expired. the first situation is depicted in figure 52, when the latency timer has not expired. preemption with a zero or expired latency timer is shown in figure 53. figure 52. master initiated termination due to pree mption and latency timer active (s5335 as master) figure 53. master initiated termination due to pree mption and latency timer expired (s5335 as master) pci clock gnt # frame irdy# trdy# s5335 latency timer 12 3 (t) (i) preemption data transferred (i) 5 4 data transferred data transferred data transferred 6 =3 =2 =1 =0 timeout sensed (i) = driven by initiator (t) = driven by target pci clock gnt # frame irdy# trdy# lat ency timer 12 3 (t ) (i) preemption dat a transferred (i) =0 =1 5 4 (i) = driven by initiator (t) = driven by target s5335 s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 99 data sheet master abort pci accesses to nonexistent or disabled targets never observe devsel# being asserted. in this situation, it is necessary for the initiator to abort the transaction (master abort). as an initiator, s5335 waits for six clock periods after asserting frame# to determine whether a master abort is required. these six clock periods allow slow targets, which may require several bus clocks before being ab le to assert devsel#, to respond. it is also possible a pci bridge device is present which employs ?subtractive? decoding. a device which does a subtractive decode asserts devsel#, claiming the cycle, when it sees that no other device has asserted it three clocks after the address phase. if devsel# is not asserted, the s5335 deasserts frame# (if asserted) upon the sixth clock period (fig- ure 54). irdy# is deasserted by the s5335 during the next clock. the occurrence of a master abort causes the s5335 to set bit 13 (master abort) of the pci sta- tus register, indicating an error condition. target-initiated termination there are situations where the target may end a trans- fer prematurely. this is called ?target-initiated termination.? target terminations fall into three catego- ries: disconnect, retry, and target abort. only the disconnect termination completes a data transfer. figure 54. master abort, no response pci clock frame # irdy# trdy# devsel# 12 3 4 5 fast device medium device slow device bridge device (subtractive decode) 67 8 (i) = driven by initiator (t) = driven by target (t) (t) (i) (i) s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 100 data sheet target disconnects there are many situations where a target may discon- nect. slow responding targets may disconnect to permit more efficient (faste r) devices to be accessed while they prepare for the nex t data phase, or a target may disconnect if it recognizes that the next data phase in a burst transfer is out of its address range. a target disconnects by asserting stop#, trdy#, and devsel# as shown in figures 55 and 56. the initiator in figure 55 responds to the disconnect condition by deasserting frame# on the following clock but does not complete the data transf er until irdy# is asserted. this situation can only occur when the s5335 is a tar- get. when the s5335 is an init iator, irdy# is always asserted during the data phase (no initiator wait states). the timing diagram in figure 56 applies to the s5335 as either a target disconnecting or an initiator with its target performing a disconnect. the s5335 performs a target disconnect if a burst access is attempted to the pci operation registers. figure 55. target disconnect example 1 (irdy# deasserted) figure 56. target disconnec t example 2 (irdy# asserted) pci clock frame # irdy# trdy# stop# devsel# 1 2 3 data transferred target disconnect identified (t) (t) (t) (i) (i) (i) = driven by initiator (t) = driven by target pci clock frame # irdy# trdy# stop# devsel# 1 2 3 data transferred target disconnect signaled, data transferred (t) (t) (t) (i) (i) (i) = driven by initiator (t) = driven by target s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 101 data sheet target requested retries when the s5335 fifo registers are accessed (s5335 as a target) and data is unavailable (empty fifo) for read transfers or cannot be accepted for write trans- fers (full fifo), the s5335 immediately terminates the cycle by requesting a retry. the s5335 also initiates a retry for pass-thru writes where the add-on has not completed the preceding pass-thru write by asserting ptrdy#, and for pass-thru reads where the add-on cannot supply data within 8 pci clocks (16 clocks for the first data phase of a burst). a retry is requested by a target asserting both stop# and devsel# while trdy# is deasserted. figure 57 shows the behavior of the s5335 when performing a target-initiated retry. target aborts a target abort termination represents an error condi- tion where no number of retries will produce a successful target access. a target abort is uniquely identified by the target deasserting devsel# and trdy# while stop# is asserted. when a target per- forms an abort, it must also set bit 11 of its pci status register. the s5335 configuration and operation regis- ters never respond with a target abort when accessed. if the s5335 encounters this condition when operating as a pci initiator, the s5335 sets bit 12 (received tar- get abort) in the pci status register. figure 58depicts a target abort cycle. target termination types are summarized in table 55. figure 57. target-initiated retry table 55. target termination types termination devsel# stop# trdy# comment disconnect on on on data is transferred. transaction needs to be reinitiated to complete. retry on on off data was not transferred. transaction should be tried later. abort off on off data was not transferred. fatal error. pci clock frame # irdy# trdy# stop# devsel# 1 2 3 initiator sequences irdy# + frame# to return to idle state 45 target retry signaled (t) (t) (t) (i) (i) (i) = driven by initiator (t) = driven by target s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 102 data sheet figure 58. target abort example figure 59. pci bus arbitration and s5335 bus ownership example pci clock frame # irdy# trdy# stop# devsel# 1 2 3 target abort identified (t) (t) (t) (i) (i) (i) = driven by initiator (t) = driven by target s5335 req# "other" req# s5335 gnt# "other" gnt# frame# ad[31:0] irdy# trdy# idle s 5 3 3 5 transaction idle (t urn- around) "other", preempting master transaction s5335 transaction(s) idle (t urn- around) 1 2 35 7 8 address dat a address dat a address data (i) = driven by initiator (t) = driven by target 46 9 s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 103 data sheet pci bus mastership when the s5335 requires pci bus mastership, it pre- sents a request via the req# signal. this signal is connected to the syste m?s pci bus arbiter. only one initiator (bus master) may control the pci bus at a given time. the bus arbiter determines which initiator is given control of the bus. control is granted to a requesting device by the arbiter asserting that device?s grant signal (gnt#). each req#/ gnt# sig- nal pair is unique to a given pci agent. after asserting req#, the s5335 assumes bus owner- ship on the first pci clock edge where its gnt# input is asserted along with frame# and irdy# deas- serted (indicating no other device is generating pci bus cycles). once ownership is established by the s5335, it maintains ownership as long as the arbiter keeps its gnt# asserted. if gnt# is deasserted, the s5335 completes the current transaction. the s5335 does this by deasserting frame# and then deasserting irdy# upon data transfer. figure 59 shows a sequence where the s5335 is granted owner- ship of the bus and then is preempted by another master before the s5335 can finish its current transaction. bus mastership latency components it is often necessary for system designers to predict and guarantee that a minimum data transfer rate is sustainable to support a partic ular application. in the design of a bus mastering application, knowledge of the maximum delay a device might encounter from the time it requests the pci bus to the time in which it is actually granted the bus is desirable. this allows the design to provide adequate data buffering. the pci specification refers to this bus request to grant delay as ?arbitration latency.? once a pci initiator has been granted the bus, the pci specification defines the delay from the grant to the new initiator?s assertion of frame# as the ?bus acqui- sition latency.? afterwards, the delay from frame# asserted to target ready (t rdy#) asserted is defined as ?target latency.? figure 60 shows a time-line depict- ing the components of pci bus access latency. there are numerous configur ation variations possible with the pci specification. a system designer can determine whether a bus mast er can support a critical, timely transfer by establishing a specific configuration and by defining these latency values. the s5335, as an initiator, produces the fastest response allowable for its bus acquisition latency (gnt# to frame# asserted). the s5335 also implements the pci master latency timer. once granted the bus, the s5335 is guaranteed ownership for a minimum amount of time defined by the master latency timer. the s5335, as an initiator, cannot control the responsiveness of a particular target nor the bus arbitration delay. the pci specification prov ides two mechanisms to control the amount of time a master may own the bus. one mechanism is through the master (masterinitiated termination). the other is by the target and is achieved through a target-initiated disconnect. bus arbitration although the pci specificati on defines the condition that constitutes bus ownership, it does not provide rules to be used by the system?s pci bus arbiter in deciding which master is to be granted the pci bus next. the arbitration priority scheme implemented by a system may be fixed, rotati onal, or custom. the arbi- tration latency is a function of the system, not the s5335. figure 60. pci bus access latency components bus access latency req# asserted gnt# asserted frame# asserted trdy# asserted --arbitration latency-- --bus acquisition-- latency --target latency-- s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 104 data sheet bus acquisition once gnt# is asserted, gi ving bus ownership to the s5335, the s5335 must wa it until the pci bus becomes idle. this delay is called bus acquisition latency and involves the state of the signals frame# and irdy#. the current bus master must complete its current transaction before the s5335 may drive the bus. table 56 depicts the four possible combinations of frame# and irdy# with their interpretation. target latency the pci specification requires that a selected target relinquish the bus should an access to that target require more than eight pci clock periods (16 clocks for the first data phase in a burst). slow targets can exist within the pci specific ation by using the target initiated retry. this prevents slow target devices from potentially monopolizing the pci bus and also allows more accurate estimations for bus access latency. target locking it is possible for a pci bus master to obtain exclusive access to a target (?locking?) through use of the pci bus signal lock#. lock# is different from the other pci bus signals because its ownership may belong to any bus master, even if it does not currently have own- ership of the pci bus. the ownership of lock#, if not already claimed by another master, may be achieved by the current pci bus master on the clock period fol- lowing the initial assertion of frame#. figure 61 describes the signal relationship for establishing a lock. the ownership of lock#, once established, per- sists even while other bus masters control the bus. ownership can only be relinquished by the master which originally established the lock. figure 61. engaging the lock# signal table 56. possible combinations of frame# and irdy# frame# irdy# description deasserted deasserted bus idle deasserted asserted the initiator is ready to comp lete the last data transfer of a transaction. asserted deasserted an initiator has a transaction in progress bu t is not able to complete the data transfer on this clock. asserted asserted an initiator has a transaction in progress and is able to complete a data transfer. pci clock frame # lock # ad[31:0] irdy# trdy# devsel# address data 1 2 3 4 5 target becomes locked lock mechanism available upon first access lock mechanism available lock established lock maintained bus idle still driven by previous owner (target is locked) 6 (t) (t) (t) (i) (i) (i) (i) = driven by initiator (t) = driven by target s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 105 data sheet targets selected with lock# deasserted during the assertion of frame# (clock period 1 of figure 61), which encounter the assertion of lock# during the following clock (clock period 2 of figure 61) are there- after considered ?locked.? a target, once locked, requires that subsequent accesses to it deassert lock# while frame# is asserted. figure 62 show a subsequent access to a locked target by the master which locked it. because lock# is owned by a single master, only that master is able to deassert it at the beginning of a transaction (allowing successful access to the locked target). a locked target can only be unlocked during the clock period following the last data transfer of a transaction when the lock# signal is deasserted. an unlocked target ignores lock# when it observes that lock# is already asserted during the first clock period of a transaction. this allows other masters to access other (unlocked) targets. if an access to a locked target is attempted by a master other than the one that locked it, the target responds with a retry request, as shown in figure 63. the s5335 responds to and supports bus masters which lock it as a target. when the s5335 is a bus master, it never attempts to lock a target, but it honors a target?s request for retry if that target is locked by another master. figure 62. access to a locked target by its owner figure 63. access atte mpt to a locked target pci clock frame # lock # ad [31:0] irdy# trdy# devsel# address data 1 2 3 4 5 condition which unlocks target locked target identifies owner data (t) (t) (i) (i) (i) (i) = driven by initiator (t) = driven by target pci clock frame # lock # ad [31:0] irdy# trdy# devsel# stop# address data 1 2 3 4 5 causes target retry termination locked target identifies that bus master is not its owner (t) (t) (t) (i) (i) (i) (i) = driven by initiator (t) = driven by target s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 106 data sheet pci bus interrupts the s5335 controller is able to generate pci bus inter- rupts by asserting the pci bus interrupt signal (inta#). inta# is a multisourced, wire-ored signal on the pci bus and is driven by an open drain output on the s5335. the assertion and deassertion of inta# have no fixed timing relationship with respect to the pci bus clock. once the s5335 asserts inta#, it remains asserted until the interrupt source is cleared by a write to the interrupt control/status register (intcsr). pci bus parity errors the pci specification defines two error-reporting sig- nals, perr# and serr#. these signals indicate a parity error condition on the signals ad[31:0], c/ be[3:0]#, and par. the valid ity of the par signal is delayed one clock period from its corresponding ad[31:0] and c/be[3:0]# sign als. even parity exists when the total number of ones in the group of signals is equal to an even number. perr# is the error- reporting mechanism for parity errors that occur during the data phase for all but pci special cycle com- mands. serr# is the error -reporting mechanism for parity errors that occur during the address phase. the timing diagram in figure 64 shows the timing rela- tionships between the signal s ad[31:0], c/be[3:0]#, par, perr# and serr#. the s5335 asserts serr# if it detects odd parity dur- ing an address phase, if enabled. the serr# enable bit is bit 8 in the s5335 pci command register. the odd parity error condition involves the state of signals ad[31:0] and c/be[3:0]# when frame# is first asserted and the par signal during the following clock. if an error is detected, the s5335 asserts serr# on the following (after par valid) clock. since many targets may observe an error on an address phase, the serr# signal is an open drain multi- sourced, wire-ored signal on the pci bus. the s5335 drives serr# low for one clock period when an address phase error is detected. once an serr error is detected by the s5335, the pci status register bit 14, system error, is set and remains until cleared through software or a hardware reset. the perr# signal is simila r to the serr# with two differences: it reports errors for the data phase and is only asserted by the device receiving the data. the s5335 drives this signal (removed from tri-state) when it is the selected target for write transactions or when it is the current master for bus read transactions. the parity error conditions are only reflected by the perr# pin if the parity error enable bit (bit 6) of the pci com- mand register is set. upon the detection of a data parity error, the detected parity error bit (bit 15) of the pci status register is se t. unlike the perr# signal pin, this status bit sets regardless of the state of the pci command register parity error enable bit. an additional status bit (bit 8) called ?data parity reported? of the pci status register is employed to report parity errors that occur when the s5335 is the bus master. the ?data parity error reported? status requires that the parity error enable bit be set in the pci command register. the assertion of perr# occurs two clock periods fol- lowing the data transfer. this two-clock delay occurs because the par signal does not become valid until the clock following the transfer, and an additional clock is provided to generate and assert perr# once an error is detected. perr# is only asserted for one clock cycle for each error sensed. the s5335 only qualifies the parity error detection during the actual data transfer portion of a data phase (when both irdy# and trdy# are asserted). figure 64. error reporting signals pci clock frame ad[31:0] c/be[3:0]# par serr# perr# 135 46 8 7 9 addr dat a byte enables dat a be's addr a a aa bb bb cmd cmd read transaction good good good good write transaction b a b a a b error error error error (t) (t) (i) (i) (i) (i) (i) (t) (t) (i) = driven by initiator (t ) = driven by target 2 s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 107 data sheet add-on bus interface this chapter describes the add-on bus interface for the s5335. the s5335 is designed to support connec- tion to a variety of mi croprocessor buses and/or peripheral devices. the add-on interface controls s5335 operation through t he add-on operation reg- isters. these registers act as the pass-thru, fifo, non-volatile memory and mailbox interfaces as well as offering control and status information. depending on the register being accessed, the inter- face may be synchronous or asynchronous. to enhance performance and simplify add-on logic design, some registers allow direct access with a sin- gle device input pin. asynchronous burst read and write fifo operations are not recommended. the fol- lowing sections describe the various interfaces to the pci bus and how they are accessed from the add-on interface. add-on operation register accesses the s5335 add-on bus interface is very similar to that of a memory or peripheral device found in a micropro- cessor-based system. a 32-bit data bus with individual read and write strobes, a chip enable and byte enables are provided. other add-on interface signals are provided to simplify add-on logic design. accesses to the s5335 registers are done primarily synchronously to bpclk. for s5335 functions that are compatible with an add-on microprocessor inter- face, it is helpful to allow an asynchronous interface, as the processor may not operate at the pci bus clock frequency. add-on interface signals the add-on interface provides a small number of sys- tem signals to allow the add-on to monitor pci bus activity, indicate status conditions (interrupts), and allow add-on bus configuration. a standard bus inter- face is provided for add-on operation register accesses. system signals bpclk and sysrst# allow the add-on interface to monitor the pci bus status. bpclk is a buffered ver- sion of the pci clock. the pci clock can operate from 0 mhz to 33 mhz. sysrst# is a buffered version of the pci reset signal, and may also be toggled by host application software through bit 24 of the bus master control/status register (mcsr). irq# is the add-on interrupt output. this signal is active low and can indicate a number of conditions. add-on interrupts may be generated from the mailbox or fifo interfaces. the exact conditions which gener- ate an interrupt are discussed in the mailbox and fifo chapters. the interrupt output is deasserted when acknowledged by an access to the add-on interrupt control/status register (a int). all interrupt sources are cleared by writing a one to the corresponding inter- rupt bit. the mode input on the add- on interface configures the datapath width for the add-on interface. mode low indicates a 32-bit data bus. mode high indicates a 16-bit data bus. for 16-bit operation, be3# is rede- fined as adr1, providing an extra address input. adr1 selects the low or high words of the 32-bit s5335 add-on operation registers. register access signals simple register accesses to the s5335 add-on opera- tion registers take two forms: synchronous to bpclk and asynchronous. the following signals are required to complete a register access to the s5335. be[3:0]# byte enable inputs. these s5335 inputs identify valid byte lanes during add-on transac- tions. when mode is set for 16-bit operation, be2# is not defined and be3# becomes adr1. adr[6:2] address inputs. these address pins identify the specific add-on operation register being accessed. when configured for 16-bit operation (mode=1), an additional input, adr1 is available to allow the 32-bit operation registers to be accessed with two 16-bit cycles. rd# read strobe input. wr# write strobe input. select# chip select input. th is input identifies a valid s5335 access. dq[31:0] bidirectional data bus. these i/o pins are the s5335 data bus. when configured for 16-bit operation, only dq[15:0] are valid. in addition, there are dedicated signals for fifo accesses (rdfifo# and wrfifo#) and pass-thru address accesses (ptadr# ). these are discussed separately in the fifo and pass-thru sections of this chapter. the internal interfaces of the s5335 allow add-on operation registers to be accessed asynchronous to bpclk (synchronous to the rising edge of the read or write strobe). the exception to this is the add-on gen- eral control/status register. this is due to the async nature of fifo status bits changing as the pci bus reads data. for pass-thru operations, the pass-thru data register accesses are synchronous to bpclk to s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 108 data sheet support burst transfers. the fifo port is also accessed synchronous to bpclk. asynchronous register accesses for many add-on applications, add-on logic does not operate at the pci bus frequency. this is especially true for add-ons implementing a microprocessor, which may be operating at a lower (or higher) fre- quency. figures 46 and 47 show asynchronous add- on operation register ac cesses. exact ac timings are detailed in the electrical and ac characteristics section. for asynchronous reads (figure 65), data is driven on the data bus when rd# is asserted. when rd# is not asserted, the dq[31:0] outputs float. a valid address and valid byte enables must be presented before cor- rect data is driven. rd# has both a minimum inactive time and a minimum active time for asynchronous accesses. for asynchronous writes (figure 66), data is clocked into the s5335 on the rising edge of the wr# input. address, byte enables, and data must all meet setup and hold times relative to the rising edge or wr#. wr# has both a minimum i nactive time and a mini- mum active time for asynchronous accesses. synchronous fifo and pass-thru data register accesses to obtain the highest data transfer rates possible, add- on logic should operate sy nchronously with the pci clock. the buffered pci cloc k (bpclk) is provided for this purpose. a synchronous interface with pass-thru mode or the fifo allows data to be transferred at the maximum pci bus bandwidth (132 mbytes/sec) by allowing burst accesses with the add-on interface. the rd# and wr# inputs become enables, using bpclk to clock data into and out of registers. this section applies only to syn chronous accesses to the fifo (afifo) and pass-thru data (aptd) registers. figures 48 and 49 show single-cycle, synchronous fifo and pass-thru operation register accesses. exact ac timings are detailed in the electrical and ac characteristics section. for synchronous reads (figure 67), data is driven onto the data bus when rd# (o r rdfifo#) is asserted. when rd# is not asserted, the dq[31:0] outputs float. the address, byte enable, and rd# inputs must meet setup and hold times relative to the rising edge of bpclk. burst reads may be performed by holding rd# low. for synchronous writes (figure 68), data is clocked into the register on the rising edge of bpclk. address, byte enables, and data must all meet setup and hold times relative to the rising edge or bpclk. burst writes may be performed by holding wr# (or wrfifo#) low. when holding wr# low, data is clocked in on each bpclk rising edge. nv memory accesses through the add-on gen - eral control/status register to access nv memory contents through the add-on general control/status register (agcsts), special considerations must be made. internally, all nv mem- ory accesses by the s5335 are synchronized to a divided-down version of the pci bus clock. because of this, if nv memory accesses are performed through the agcsts register, the regi ster access must be syn- chronized to bpclk. the rising edge rd# or wr# is still used to clock data, but these inputs along with the address and byte enables are synchronized to bpclk. accesses to agcsts for monitoring fifo or mailbox status, etc., may be done asynchronous to bpclk. mailbox bus interface the mailbox register names may need some clarifica- tion. for the add-on interface, an outgoing mailbox refers to a mailbox sending information to the pci bus. an incoming mailbox refers to a mailbox receiving information from the pci bu s. an outgoing mailbox on the add-on interface is, internally, the same as the corresponding incoming mailbox on the pci interface and vice-versa. s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 109 data sheet figure 65. asynchronous add-on operation register read figure 66. asynchronous add-on operation register write be[3:0]# dq[31:0] select# rd# adr[6:2] valid byte enables valid address valid data out be[3:0]# dq[31:0] select# wr# adr[6:2] valid byte enables valid address valid data in s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 110 data sheet figure 67. synchronous fifo or pass-thru data register read figure 68. synchronous fifo or pass-thru data register write bpclk dq[31:0] rd# rdfifo# select# adr[6:2] be[3:0]# valid 2 valid data out 2 valid 1 valid data out 1 bpclk dq[31:0] wr# wrfifo# select# adr[6:2] be[3:0]# valid 2 valid data in 2 valid 1 valid data in 1 s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 111 data sheet mailbox interrupts mailboxes can be configured to generate add-on interrupts (irq#) and/or allow the add-on to generate pci interrupts (inta#). mailbox empty/full status con- ditions be can used to interrupt the add-on or pci host to indicate some action is required. an individual mailbox byte is selected to generate an interrupt when accessed. an outgoing mailbox becoming empty or an incoming mailbox becoming full asserts the interrupt output (if enabled). when used with a serial nv memory boot device, the mailboxes also provide a way to generate pci inter- rupts (inta#) through hardware. when a serial nv memory boot device is used, the device pin functions ea0 - ea8 are redefined. these pins then provide direct, external access to the add-on outgoing mail- box 4, byte 3 (which is also pci incoming mailbox 4, byte 3). fifo bus interface the fifo register on the add-on interface may only be accessed synchronously or asynchronously. asyn- chronous burst read and write fifo operations are not recommended. location 45h, bits 6 and 5 in the nv memory boot device must be programmed to a ?0? for correct operation. fifo direct access inputs rdfifo# and wrfifo# are referred to as fifo ?direct access? inputs. asserting rdfifo# is function- ally identical to accessi ng the fifo with rd#, select#, be[3:0]#, and adr[6:2]. asserting wrfifo# is functionally identical to accessing the fifo with wr#, select#, be[3:0]#, and adr[6:2]. rd# and wr# must be deas serted when rdfifo# or wrfifo# is asserted, but select# may be asserted. these inputs automatically drive the address (internally) to 20h and assert all byte enables. the adr[6:2] and be[3:0]# inputs are ignored when using the fifo direct access inputs. rdfifo# and wrfifo# are useful for add-on designs which cas- cade an external fifo into the s5335 fifo or use dedicated external logic to access the fifo. direct access signals always access the fifo as 16- bits or 32-bits, whatever the mode pin is configured for. for 16-bit mode, two consecutive accesses fill or empty the 32-bit fifo register. fifo status signals the fifo status signals indicate to the add-on logic the current state of the s5335 fifo. a fifo status change caused by a pci fifo access is reflected one pci clock period after th e pci access is completed (trdy# asserted). a fifo status change caused by an add-on fifo access is reflected immediately (after a short propagation delay) after the access occurs. for add-on accesses, fifo status is updated after the ris- ing edge of bpclk for synchronous interfaces or after the rising edge of the read or write strobe for asyn- chronous interfaces. fifo control signals for add-on initiated pci bu s mastering, the fifo sta- tus reset controls fwc# (add-on to pci fifo clear) and frc# (pci to add-on fifo clear) are available. fwc# and frc# must be asserted for a minimum of one bpclk period to be recognized. these inputs are sampled at the rising edge of bpclk. these inputs should not be asserted unless the fifo is idle. assert- ing a fifo status reset input during a pci or add-on fifo access results in indeterminate operation. for add-on initiated bus master transfers, amren (add-on bus master read enable) and amwen (add- on bus master write enable) are used, in conjunction with the appropriate fifo status signals, to enable the s5335 to assert its pci bus request (req#). pass-thru bus interface the s5335 pass-thru interface is synchronous. the add-on pass-thru addres s (apta) and add-on pass-thru data (aptd) registers may be accessed pseudo-synchronously. although bpclk is used to clock data into and out of the pass-thru registers, accesses may be performed asynchronously. for reads, apta or aptd data remains valid as long as rd# (or ptadr#) is asserted. a new value is not driven until ptrdy# is asserted by add-on logic. fo r writes to aptd, data is clocked into the s5335 on every bpclk rising edge, but is not passed to the pci bus until ptrdy# is asserted. ptrdy# must by synchronized to bpclk. pass-thru status indicators the pass-thru status indicators indicate that a pass- thru access is in process and what action is required by the add-on logic to co mplete the a ccess. all pass- thru status indicators ar e synchronous with the pci clock. pass-thru control inputs some pass-thru implementations may require an address corresponding to the pass-thru data. the add-on pass-thru address register (apta) contains the pci address for the pass-thru cycle. to allow access to the pass-thru address without generating an add-on read cycle, ptadr# is provided. ptadr# is a direct access input for the pass-thru address. s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 112 data sheet asserting ptadr# is functionally identical to access- ing the pass-thru address register with rd#, select#, be[3:0]#, and adr[6:2]. rd# and wr# must be deasserted when ptadr# is asserted, but select# may be asserted. these inputs automati- cally drive the address (internally) to 28h and assert all byte enables. the adr[6:2] and be[3:0]# are ignored when using the ptadr# direct access input. when ptadr# is asserted, the contents of the apta register are immediately driven onto the add-on data bus. the ptadr# direct access signal accesses the pass- thru address register as 16-bits or 32-bits, whatever the mode pin is configured for. for 16-bit mode, ptadr# only presents the lower 16-bits of the apta register. ptrdy# indicates that the add-on has completed the current pass-thru access. mu ltiple add-on reads or writes may occur to the pass-thru data (aptd) regis- ter before asserting ptrdy#. this may be required for 8-bit or 16-bit add-on interfaces using multiple accesses to the 32-bit pass-thru data register. in some cases, the add-on bus may be 32-bits, but logic may require multiple bpclk periods to read or write data. in this situation, accesses may be extended by holding off ptrdy#. ptrdy# must be synchronized to bpclk. non-volatile memory interface the s5335 allows read and write access to the nv memory device used for configuration. reads are nec- essary during device initia lization as configuration information is downloaded into the s5335. if an expan- sion bios is implemented in the nv memory, the host transfers (shadows) the code into system dram. writes are useful for in-field updates to expansion bios code. this allows software to update the nv memory contents without altering hardware. non-volatile memory interface signals for serial nv memory devic es, there are only two sig- nals used to interface with nv memory. scl is the serial clock, and sda is the serial data line. the func- tionality of these signals is described in-detail in the pin description section of this book. the designer does not need to generate the timings for scl and sda. the s5335 automatically performs the correct serial access when programmed for serial devices. for byte-wide nv memory devices, there is an 8-bit data bus (eq7:0), and a 16-bit address bus (ea15:0) dedicated for the nv memory interface. when a serial nv memory is implemented, many of these pins have alternate functions. the s5335 also has read (erd#) and write (ewr#) outputs to drive the oe# and wr# inputs on a byte-wide nv memory. the designer does not need to generate the timings for these outputs. the s5335 automatically perf orms the read and write accesses when programmed for byte wide devices. accessing non-volatile memory the nv memory, if implemented, can be accessed through the pci interface or the add-on interface. accesses from both the pci side and the add-on side must be synchronous with th e pci clock (bpclk for the add-on). accesses to the nv memory from the pci interface are through the bus master control/status register (mcsr) pci operation register. accesses to the nv memory from the add-on interface are through the add-on general control/status regis- ter (agcsts) add-on operation register. accesses to the mcsr register are from the pci bus and are, therefore, automatically synch ronous to the pci clock. accesses to the agcsts register from the add-on s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 113 data sheet some nv memories may contain expansion rom bios code for use by the host software. during initial- ization, the expansion bios is located within system memory. the starting location of the nv memory is stored in the expansion rom base address register in the s5335 pci configurat ion registers. a pci read from this region results in the s5335 performing four consecutive byte access to the nv memory device. writes to the nv memory are not allowed by writing to this region. writes to the nv memory must be per- formed as described below. the s5335 contains two latches within the mcsr reg- ister to control and access the nvram. one is an 8 bit latch called the nvram address/data register which is used to hold nvram addre ss and data information. the other is a 3 bit latch called the nvram access control register which is used to direct the address and data information and to control the nvram itself. reading or writing to the nvram is performed through bits d31:29 of this register. these bits are enable and decode controls rather than a command or instruction to be executed. d31 of this register is the primary enable bit which allows all accesses to occur. when written to a ?1?, d31 enables the decode bits d30 and d29 to direct the data contained in the address/data latch, d23:16, to the low address, high address or data latches. d31 should be thought of as ?opening a door? where as long as d31 = 1, then the door is open for address or data information to be altered. the table on page 5-16 of the s5335 data book shows the d31:29 bit combinations for reading, writing, and loading ad- dress/data information. additionally, d31 doubles as an s5335 status bit. a ?1? indicates that the s5335 is currently busy reading or writing to the nvram. a ?0? indicates a complete or inactive state. for the examples below, we will assume the s5335 is i/o mapped with a base address of fc00h. these examples will read one byte of the vendor id and write one byte to the vendor id. this example will write 1 byte from nv ram location 0040h and read it back: in out out out out out out out in out in in fc00h + 3fh (offset of nvram access control register) until d31 = 0 (not busy). fc00h + 3fh an 80h (cmd to load the low address byte). this sets decode bits and opens door for low address latch. fc00h + 3eh (offset of address/data register) 40h (the low byte of the address desired) 40h goes into latch but is not latched yet. fc00h + 3fh an a0h (cmd to load the high address byte). this latches the low address through changing the decode bits and opens the door for the high address latch. fc00h + 3eh a 00h (the high byte of the address desired). 00h goes into the latch but is not latched yet. fc00h + 3fh an 00h (inactive cmd). this latches the high address through the disabling d31, ?closes the door?. fc00h + 3eh data (the data byte to be written). data byte goes into the latch but is not latched yet. fc00h + 3fh a c0h (cmd to write the data byte). this latches t he data byte through changing the decode bits and begins to write nvram data operation. fc00h + 3fh until d31 = 0 (not busy). fc00h + 3fh an e0h (cmd to read the address latched). fc00h + 3fh until d31 = 0 (not busy). fc00h + 3eh the data . s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 114 data sheet notes: 1. latched addresses do not automatically increment after a read or write. they must be loaded with new values. 2. latched addresses remain after reads and writes. it is al lowable to only update one address byte for the next access. 3. a processor may perform a one word write to load an address byte and control command simultaneously. this example will read 1 byte from nvram location 0040h: in out out out out out in in fc00h + 3fh (offset of nvram access control register) until d31 = 0 (not busy). fc00h + 3fh an 80h (cmd to load the low address byte). this sets decode bits and opens door for low address latch. fc00h + 3eh (offset of address/data register) 40h (the low byte of the address desired) 40h goes into latch but is not latched yet. fc00h + 3fh an a0h (cmd to load the high address byte). this latches the low address through changing the decode bits and opens the door for the high address latch. fc00h + 3eh a 00h (the high byte of the address desired) 00h goes into latch but is not latched yet. fc00h + 3fh an e0h (cmd to read nvram data). this latches the high address through changing the decode bits and begins to read the nvram data operation. fc00h + 3fh until d31 = 0 (not busy). fc00h + 3eh the data. this example will read 1 byte from nvram location 0041h and contains an extra step to demonstrate d31 operation: in out out out out out out in in fc00h + 3fh (offset of nvram access control register) until d31 = 0 (not busy). fc00h + 3fh an 80h (cmd to load the low address byte). this sets decode bits and opens the door for low address latch. fc00h + 3eh (offset of address/data register) 40h (the low byte of the address desi red) 40h goes into latch but is not latched yet. fc00h + 3eh (offset of address/data register) 41h (the low byte of the address desi red) 41h goes into latch but is not latched yet. fc00h + 3fh an a0h (cmd to load the high address byte). this latches the low address through changing the decode bits and opens the door for the high address latch. fc00h + 3eh 00h (the high byte of the address desired) 00h goes into latch but is not latched yet. fc00h + 3fh an e0h (cmd to read the address latched). this latches the high address through changing the decode bits and begins the read nvram data operation. fc00h + 3fh until d31 = 0 (not busy). fc00h + 3eh the data. s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 115 data sheet nv memory device timing requirements for serial nv memory devices, the serial clock output frequency is the pci clock frequency divided by 512. this is approximately 65 khz (with a 33 mhz pci clock). any serial memory dev ice that operates at this frequency is compatible with the s5335. for byte-wide accesses, the s5335 generates the waveforms shown in figures 50 and 51. figure 69 shows an nv memory read operation. figure 70 shows an nv memory write operation. read operations are always the same length. write operations, due to the characteristics of reprogrammable nv memory devices, may be controlled through a programming sequence. figure 69. nv memory read operation memory device requireme nts for read accesses timing spec. t = 30 ns read cycle time 8t(max) 240 ns address valid to data valid 7t?10(max) 200 ns address valid to read active t(max) 30 ns read active to data valid 6t?10(max) 170 ns read pulse width 6t(max) 180 ns data hold from read inactive ? 2 ns data valid eq[7:0] (input) ea[15:0] (output) erd# (output) address valid t 35 t 36 t 37 t 39 t 38 t 41 t 40 s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 116 data sheet figure 70. nv memory write operation memory device requireme nts for write accesses timing spec. t = 30 ns write cycle time 8t note 1 address valid to write active t(max) 30 ns data valid to write inactive 6t+10(max) 190 ns data hold from write inactive t(max) 30 ns write pulse width 6t(max) 180 ns write inactive note 2 2 ns data valid eq[7:0] (output) ea[15:0] (output) ewr# (output) address valid t 42 t 43 t 44 t 39 t 46 t 45 t 38 s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 117 data sheet mailbox overview the s5335 has eight 32-bit mailbox registers. the mailboxes are useful for passing command and status information between the add-on and the pci bus. the pci interface has four incoming mailboxes (add-on to pci) and four outgoing mailboxes (pci to add-on). the add-on interface has four incoming mailboxes (pci to add-on) and four outgoing mailboxes (add-on to pci). the pci incoming and add-on outgoing mail- boxes are the same, internally. the add-on incoming and pci outgoing mailboxes are also the same, internally. the mailbox status may be monitored in two ways. the pci and add-on interfaces each have a mailbox status register to indicate the empty/full status of bytes within the mailboxes. the mailboxes may also be con- figured to generate interrupts to the pci and/or add- on interface. one outgoing and one incoming mailbox on each interface can be configured to generate interrupts. functional description figure 71 shows a block diagram of the pci to add-on mailbox registers. add-on incoming mailbox read accesses pass through an output interlock latch. this prevents a pci bus write to a pci outgoing mailbox from corrupting data being read by the add-on. figure 72 shows a block diagram of the add-on to pci mail- box registers. pci incoming mailbox reads also pass through an interlocking mechanism. this prevents an add-on write to an outgoing mailbox from corrupting data being read by the pci bus. the following sections describe the mailbox flag functionality and the mailbox interrupt capabilities. figure 71. block diagram - pci to add-on mailbox register figure 72. block diagram - add-on to pci mailbox register mailbox register add-on bus "incoming mailbox" select output interlock latch output driver add-on bus mailbox full s q d "o" load enable read enable en en add-on rd# select# empty/full ff q d q d pci bus "outgoing mailbox" selected read enable p c i b u s i n t e r f a c e a d d - o n i n t e r f a c e "incoming mailbox" mailbox register pci "incoming mailbox" select output interlock latch add-on bus "outgoing mailbox" wr# select# pci bus "incoming mailbox" register decode of adr[6:2] be[3:0]# mailbox full "o" pci read pulse empty/full ff add-on write pulse selected read pulse en q s d qd qd p c i b u s i n t e r f a c e a d d - o n i n t e r f a c e s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 118 data sheet mailbox empty/full conditions the pci and add-on interfaces each have a mailbox status register. the pci mailbox empty/full status (mbef) and add-on mailbox empty/full status (ambef) registers indicate the status of all bytes within the mailbox registers. a write to an outgoing mailbox sets the status bits for that mailbox. the byte enables determine which bytes within the mailbox become full (and which status bits are set). an outgoing mailbox for one interface is an incoming mailbox for the other. therefore, incoming mailbox sta- tus bits on one interface are identical to the corresponding outgoing mailbox status bits on the other interface. the following list shows the relation- ship between the mailbox registers on the pci and add-on interfaces. a write to an outgoing mailbox also writes data into the incoming mailbox on the other interface. it also sets the status bits for the outgoing mailbox and the status bits for the incoming mailbox on the other interface. reading the incoming mailbox clears all correspond- ing status bits in the a dd-on and pci mailbox status registers (ambef and mbef). for example, a pci write is performed to the pci out- going mailbox 2, writing bytes 0 and 1 (be0# and be1# asserted). reading t he pci mailbox empty/full status register (mbef) indicates that bits 4 and 5 are set. these bits indicate that outgoing mailbox 2, bytes 0 and 1 are full. reading the add-on mailbox empty/ full status register (ambef) shows that bits 4 and 5 in this register are also set, indicating add-on incom- ing mailbox 2, bytes 0 and 1 are full. an add-on read of incoming mailbox 2, bytes 0 and 1 clears the status bits in both the mbef and ambef status registers. to reset individual flags in the mbef and ambef reg- isters, the corresponding by te must be read from the incoming mailbox. the pci and add-on mailbox sta- tus registers, mbef and ambef, are read-only. mailbox flags may be globally reset from either the pci interface or the add-on inte rface. the pci bus master control/status register (mcsr) and the add-on gen- eral control/status register (agcsts) each have a bit to reset all of the mailbox status flags. mailbox interrupts the designer has the option to generate interrupts to the pci and add-on interfaces when specific mailbox events occur. the pci and add-on interfaces can each define two conditions where interrupts may be generated. an interrupt can be generated when an incoming mailbox becomes full and/or when an outgo- ing mailbox becomes empty. a specific byte within a specific mailbox is selected to generate the interrupt. the conditions defined to generate interrupts to the pci interface do not have to be the same as the condi- tions defined for the add-on interface. interrupts are cleared through software. for incoming mailbox interrupts, when the specified byte becomes full, an interrupt is generated. the inter- rupt might be used to indicate command or status information has been provided, and must be read. for pci incoming mailbox interrupts, the s5335 asserts the pci interrupt, inta#. for add-on incoming mail- box interrupts, the s5335 asserts the add-on interrupt, irq#. for outgoing mailbox interrupts, when the specified byte becomes empty, an interrupt is generated. the interrupt might be used to indicate that the other inter- face has received the last information sent and more may be written. for pci outgoing mailbox interrupts, the s5335 asserts the pci interrupt, inta#. for add- on outgoing mailbox interrupts, the s5335 asserts the add-on interr upt, irq#. pci interface add-on interface outgoing mailbox1 outgoing mailbox 2 outgoing mailbox 3 outgoing mailbox 4 incoming mailbox 1 incoming mailbox 2 incoming mailbox 3 incoming mailbox 4 pci mailbox empty/full = = = = = = = = = incoming mailbox 1 incoming mailbox 2 incoming mailbox 3 incoming mailbox 4 outgoing mailbox 1 outgoing mailbox 2 outgoing mailbox 3 outgoing mailbox 4 add-on mailbox empty/ full s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 119 data sheet add-on outgoing mailbox 4, byte 3 access pci incoming mailbox 4, byte 3 (add-on outgoing mailbox 4, byte 3) does not function exactly like the other mailbox bytes. when an a serial nv memory boot device or no external boot device is used, the s5335 pins ea7:0 are redefined to provide direct external access to add-on outgoing mailbox 4, byte 3. ea8 is redefined to provide a load clock which may be used to generate a pci interrupt. the pins are redefined as follows: if the s5335 is programmed to generate a pci inter- rupt (inta#), on an add-on write to outgoing mailbox 4, byte 3, a rising edge on embclk generates a pci interrupt. the bits emb7:0 can be read by the pci bus interface by reading the pci incoming mailbox 4, byte 3. these bits are useful to indicate various conditions which may have caused the interrupt. when using the s5335 with a byte-wide boot device, the capability to generate pci interrupts with add-on hardware does not exist. in this configuration, pci incoming mailbox 4, byte 3 (add-on incoming mailbox 4, byte 3) cannot be used to transfer data from the add-on - it always returns zeros when read from the pci bus. this mailbox byte is sacrificed to allow the added functionality provided when a byte-wide boot device is not used. bus interface the mailboxes appear on the add-on and pci bus interfaces as eight operatio n registers. four are outgo- ing mailboxes, four are incoming mailboxes. the mailboxes may be used to generate interrupts to each of the interfaces. the following sections describe the add-on and pci bus interfaces for the mailbox registers. pci bus interface the mailboxes are only accessible with the s5335 as a pci target. the mailbox operation registers do not support burst accesses by an initiator. a pci initiator attempting to burst to the mailbox registers causes the s5335 to respond with a target disconnect with data. pci writes to full outgoing mailboxes overwrite data currently in that the mail box. pci reads from empty incoming mailboxes return the data that was previ- ously contained in the mailbox. neither of these situations cause a target retry or abort. pci incoming and outgoing mailbox interrupts are enabled in the interrupt control/status register (intcsr). the mailboxes can generate a pci inter- rupt (inta#) under two conditions (individually enabled). for an incoming mailbox full interrupt, inta# is asserted on the pci clock rising edge after the add- on mailbox write completes. for an outgoing mailbox empty interrupt, inta# is asserted on the pci clock rising edge after the add-on mailbox read completes (the rising edge of rd#). inta# is deasserted on the next pci clock rising edge after the pci access to clear the mailbox interrupt completes (trdy# deasserted). add-on bus interface the add-on mailbox interface behaves similar to the pci bus interface. add-on wr ites to full outgoing mail- boxes overwrite data current ly in that mailbox. pci reads from empty incoming mailboxes return the data that was previously contained in the mailbox. add-on incoming and outgoing mailbox interrupts are enabled in the add-on interrupt control/status regis- ter (aint). the mailboxes can generate the add-on irq# interrupt under two conditions (individually enabled). for an incoming mailbox full interrupt, irq# is asserted one pci clock period after the pci mailbox write completes (trdy# deasserted). for an outgoing mailbox empty interrupt, irq# is asserted one pci clock period after the pci mailbox read completes (trdy# deasserted). irq# is deasserted immediately when the add-on clears the mailbox interrupt. when the s5335 is used with a serial nv memory boot device or no external boot device, the device pins ea8:0 are redefined. ea7:0 become emb7:0 data inputs and ea8 becomes embclk, a load clock. this configuration allows the add-on to generate pci inter- rupts with a low-to-high transition on embclk. the pci incoming mailbox interrupt must be enabled and set for mailbox 4, byte3 in the pci interrupt control/ status register (intcsr). embclk should begin high and be pulsed low, then high to be recognized. the rising edge of embclk generates the interrupt. the rising edge of embclk also latches in the values on emb7:0. the s5335 interrupt logic must be cleared (inta# deasserted) through intcsr before further embclk interrupts are recognized. signal pin add-on outgoing mailbox ea0/emb0 ea1/emb1 ea2/emb2 ea3/emb3 ea4/emb4 ea5/emb5 ea6/emb6 ea7/emb7 ea8/embclk mailbox 4, bit 24 mailbox 4, bit 25 mailbox 4, bit 26 mailbox 4, bit 27 mailbox 4, bit 28 mailbox 4, bit 29 mailbox 4, bit 30 mailbox 4, bit 31 mailbox 4, byte 3 load clock s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 120 data sheet 8-bit and 16-bit add-on interfaces some add-on designs may implement an 8-bit or 16- bit bus interface. the mailboxes do not require a 32-bit add-on interface. for 8-bit interfaces, the 8-bit data bus may be externally connected to all four bytes of the 32-bit add-on interface (dq 31:24, 23:16, 15:8, 7:0 are all connected). the add-on device reading or writing the mailbox regist ers may access all mailbox bytes by cycling through the add-on byte enable inputs. a similar solution applies to 16-bit add-on buses. this solution wor ks for add-ons which always use just 8-bit or just 16-b it accesses. if the mode pin is high, indicating a 16-bit add-on interface, the previ- ous solution may be modified for an 8-bit interface. the difference is that adr1 must be toggled after the first two accesses to steer the s5335 internal data bus to the upper 16-bits of the mailboxes. configuration the pci interface and the add-on interface each have four incoming mailboxes (imbx or aibmx) and four outgoing mailboxes (ombx or aombx) along with a single mailbox status regi ster (mbef or ambef). out- going mailboxes are read/write, incoming mailboxes and the mailbox status registers are read-only. the following sections discuss the registers associ- ated with the mailboxes and accesses required for different modes of mailbox operation. mailbox status every byte in each mailbox has a status bit in the mail- box empty/full status registers (mbef and ambef). writing a particular byte into an outgoing mailbox sets the corresponding status bit in both the mbef and ambef registers. a read of a ?full? byte in a mailbox clears the status bit. the mbef and ambef are read- only. status bits cannot cleared by writes to the status registers. the s5335 allows the mailbox status bits to be reset through software. the bus master control/status (mcsr) pci operation register and the add-on gen- eral control/status (agcsts) add-on operation register each have a bit to reset mailbox status. writ- ing a ?1? to mailbox flag reset bit in the mcsr or the agcsts register immediately clears all bits in the both the mbef and ambef registers. writing a ?0? has no effect. the mailbox flag reset bit is write-only. the flag bits should be monitored when transferring data through the mailboxes. checking the mailbox sta- tus before performing an operation prevents data from being lost or corrupted. the following sequences are suggested for pci mailbox operations using status polling (interrupts disabled): reading a pci incoming mailbox: 1. check mailbox status. read the mailbox status register to determine if any information has been passed from the add- on interface. mbef bits 31:16 if a bit is set, valid data is contained in the corresponding mailbox byte. 2. read mailbox(es). read the mailbox bytes which mbef indicates are full. this automatically resets the status bits in the mbef and ambef registers. imbx bits 31:0 mailbox data. writing a pci outgoing mailbox: 1. check mailbox status. read the mailbox stat us register to determine if information previously written to the mailbox has been read by the add-on interface. writes to full mailbox bytes overwrite data cu rrently in the mailbox (if not already read by the add-on interface). repeat until the byte(s) to be written are empty. mbef bits 15:0 if a bit is set, valid data is contained in the corresponding mailbox byte and has not been read by the add-on. 2. write mailbox(es). write to the outgoing mailbox byte(s). ombx bits 31:0 mailbox data. s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 121 data sheet mailbox operations for the add-on interface are functi onally identical. the followi ng sequences are suggested for add-on mailbox operations using stat us polling (interrupts disabled): mailbox interrupts although polling status is useful, in so me cases, polling requires continuous actions by the processor reading or writing the mailbox. mailbox interrupt capabilities are pr ovided to avoid much of the processor overhead required by continuously polling status bits. the add-on and pci interface can each generate interrupts on an incoming mailbox condition and/or an outgoing mailbox condition. these can be individually enabled/disabl ed. a specific byte in one incoming mailbox and one outgoing mailbox is identified to generate the interrupt(s). the tasks required to setup mailbox interrupts are shown below: reading an add-on incoming mailbox: 1. check mailbox status. read the mailbox status register to de termine if any information has be en passed from the pci interface . ambef bits 15:0 if a bit is set, valid data is contained in the corre- sponding mailbox byte. 2. read mailbox(es). read the mailbox bytes which ambef indicates are full. this automatically resets the status bits in the ambef and mbef registers. aimbx bits 31:0 mailbox data. writing an add-on outgoing mailbox: 1. check mailbox status. read the mailbox status register to det ermine if information previously written to the mailbox has been read by the pci interface. writes to full mailbox byte s overwrite data currently in the mailbox (if not already read by the pci interface). repeat until the byte(s) to be written are empty. ambef bits 31:16 if a bit is set, valid data is contained in the corre- sponding mailbox byte and has not been read by the pci bus. 2. write mailbox(es). write to the outgoing mailbox byte(s). aombx bits 31:0 mailbox data. enabling pci mailbox interrupts: 1. enable pci outgoing mailbox interrupts. a specific byte within one of the outgoing mailbox es is identified to assert inta# when read by the add-on interface. intcsr bit 4 enable outgoing mailbox interrupts intcsr bits 3:2 identify mailbox to generate interrupt intcsr bits 1:0 identify mailbox byte to generate interrupt 2. enable pci incoming mailbox interrupts. a specific byte wi thin one of the incoming mailboxes is identified to assert inta# when written by the add-on interface. intcsr bit 12 enable incoming mailbox interrupts intcsr bits 11:10 identify mailbox to generate interrupt intcsr bits 9:8 identify mailbox byte to generate interrupt s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 122 data sheet once interrupts are enabled, the interrupt service rout ine must access the mailbox es and clear the interrupt source. a particular application may not require all of t he steps shown. for instance, a design may only use incom- ing mailbox interrupts and not require support for outgoing mail box interrupts. the interr upt service routine tasks are shown below: enabling add-on mailbox interrupts: 1. enable add-on outgoing mailbox interrupts. a specific byte within one of the outgoing mailboxes is identified to assert irq# when read by the pci interface. aint bit 12 enable outgoing mailbox interrupts aint bits 11:10 identify mailbox to generate interrupt aint bits 9:8 identify mailbox byte to generate interrupt 2. enable add-on incoming mailbox interrupts. a specific byte within one of the incoming mailboxes is identified to assert irq# when written by the pci interface. aint bit 4 enable incoming mailbox interrupts aint bits 3:2 identify mailbox to generate interrupt aint bits 1:0 identify mailbox byte to generate interrupt with either the add-on or pci interface, these two steps ca n be performed with a single access to the appropriate register. they are shown separately here for clarity. servicing a pci mailbox interrupt (inta#): 1. identify the interrupt source(s). multiple interrupt sources are available on the s5335. the interrupt service routine must verify that a mailbox generated the interrupt (and not some other interrupt source). intcsr bit 16 pci outgoing mailbox interrupt indicator intcsr bit 17 pci incoming mailbox interrupt indicator 2. check mailbox status. the mailbox status bits indicate which mailbox bytes must be read or written. mbef bits 31:16 full pci incoming mailbox bytes mbef bits 15:0 empty pci outgoing mailbox bytes 3. access the mailbox. based on the contents of mbef, mailboxes are read or written. reading an incoming mailbox byte clears the corresponding status bit in mbef. ombx bits 31:0 pci outgoing mailboxes imbx bits 31:0 pci incoming mailboxes 4. clear the interrupt source. the pci inta# signal is deassert ed by clearing the interrupt r equest. the request is cleared by writing a ?1? to the appropriate bit. intcsr bit 16 clear pci outgoing mailbox interrupt intcsr bit 17 clear pci incoming mailbox interrupt s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 123 data sheet servicing an add-on mailbox interrupt (irq#): 1. identify the interrupt source(s). multiple interrupt sources are available on the s5335. the interrupt service routine must verify that a mailbox generated the interrupt (and not some other interrupt source). aint bit 16 add-on incoming mailbox interrupt indicator aint bit 17 add-on outgoing mailbox interrupt indicator 2. check mailbox status. the mailbox status bits indicate which mailbox bytes must be read or written. ambef bits 31:16 empty add-on outgoing mailbox bytes ambef bits 15:0 full add-on incoming mailbox bytes 3. access the mailbox. based on the cont ents of ambef, mailboxes are read or wr itten. reading an incoming mailbox byte clears the correspo nding status bit in ambef. aimbx bits 31:0 add-on incoming mailboxes aombx bits 31:0 add-on outgoing mailboxes 4. clear the interrupt source. the add-on irq# signal is d easserted by clearing the interrupt request. the request is cleared by writing a ?1? to the appropriate bit. aint bit 16 clear add-on incoming mailbox interrupt aint bit 17 clear add-on outgoing mailbox interrupt in both cases, step 3 involves accessing the mailbox. to allow the incoming mailbox interrupt logic to be cleared, the mailbox status bit must also be cleared. reading an incoming mailbox clears the status bits. another op tion for clearing the status bit s is to use the mailbox flag reset bit in the mcsr and agcsts re gisters, but this clears all stat us bits, not just for a single mailbox or mailbox byte. for outgoing mailbox interrupts, the read of a mailbox register is what generated the interrupt; this ensures the status bits are already clear. s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 124 data sheet s5335 fifo overview the s5335 has two internal fifos. one fifo is for pci bus to add-on bus, the other fifo is for add-on bus to pci bus transfers. each of these has eight 32- bit registers. the fifos are both addressed through a single pci/add-on operation register offset, but which internal fifo is accessed is determined by whether the access is a read or write. the fifo may be either a pci target or a pci initiator. as a target, the fifo allows a pci bus master to access add-on data. the fifo also allows the s5335 to become a pci initiator. read and write address reg- isters and transfer count registers allow the s5335 to perform dma transfers across the pci bus. the fifo may act as initiator and a target at different times in the same application. the fifo can be configured to support various add- on bus configurations. fifo status and control signals allow simple cascading into an external fifo, the add- on bus can be 8-, 16-, or 32-bits wide, and data endian conversion is optional to support any type of add-on cpu. pci and add-on interrupt capabilities are available to support bus mastering through the fifo. functional description the s5335 fifo interface allows a high degree of functionality and flexibilit y. different fifo manage- ment schemes, endian conversion schemes, and advance conditions allow for a wide variety of add-on interfaces. applications ma y implement the fifo as either a pci target or program it to enable the s5335 to be a pci initiator (bus master). the following sec- tions describe, on a functional level, the capabilities of the s5335 fifo interface. fifo buffer management and endian conversion the s5335 provides a high degree of flex ibility for con- trolling the data flow through the fifo. each fifo (pci to add-on and add-on to pci) has a specific fifo advance condition. for fifo writes, the byte which signifies a location is full is configurable. for fifo reads, the byte which signifies a location is empty is configurable. this ab ility is useful for transfer- ring data through the fifo with add-ons which are not 32-bits wide. endian conversion may also be per- formed on data passing through the fifo. fifo advance conditions the specific byte lane us ed to advance the fifo, when accessed, is determined individually for each fifo interface (pci and add-on). the control bits to set the advance condition are d29:26 of the interrupt control/status register (intcsr) in the pci opera- tion registers (figure 73 ). the default fifo advance condition is set to byte 0. with the default setting, a write to the fifo with be0# asserted indicates that the fifo location is now full, advancing the fifo pointer to the next location. be0# does not have to be the only byte enable asserted. note, the fifo advance condi- tion may be different for the pci to add-on fifo and the add-on to pci fifo directions. figure 73. intcsr fifo advance and endian control bits intcsr 0 0 1 1 0 no conversion (default) 1 16 bit endian conv. 0 32 bit endian conv. 1 64 bit endian conv fifo advance control pci interface 0 0 byte 0 (default) 0 1 byte 1 1 0 byte 2 1 1 byte 3 fifo advance control add-on interface 0 0 byte 0 (default) 0 1 byte 1 1 0 byte 2 1 1 byte 3 pci to add-on fifo pci add-on dword toggle 0 = bytes 0-3 (default) 1 = byte 4-7 (note1) add-on to pci fifo add-on pci dword toggle 0 = bytes 0-3 (default) 1 = byte 4-7 (note1) note 1: d24 and d25 must be also "1" 31 30 29 28 27 26 25 24 s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 125 data sheet the configurable fifo advance condition may be used to transfer data to and from add-on interfaces which are not 32-bits wide. for a 16-bit add-on bus, the add-on to pci fifo advance condition can be set to byte 2. this allows a 16-bit write to the lower 16-bits of the fifo register (bytes 0 and 1) and a second write to the upper 16-bits of the fifo register (bytes 2 and 3). the fifo does not advance until the second access. this allows the add-on to operate with 16-bit data, while the pci bus maintains a 32-bit data path. figure 74. 16-bit endian conversion notes: 1. during operation, the intcsr fifo advance condition bits (d29:26) should only be changed when the fifo is empty and is idle on both the add-on and pci interfaces. endian conversion bits d31:30 and d25:24 of the intcsr pci operation register control endian conversion operations for the fifo (figure 73). when endian conversion is per- formed, it affects data pa ssing in either direction through the fifo interface. figures 74 and 75 show 16-bit and 32-bit endian conversion. it is important to note that endian conversion is performed on data be- fore it enters the fifo. this affects the fifo advance condition. example: the fifo is configured to perform 32-bit endian conversion on data, and the fifo advance condition is set to byte 0. byte 3 is writ- ten into the fifo (be3# a sserted). after the endian conversion, byte 3 becomes byte 0, and the fifo advances. this behavior must be considered when not performing full 32-bit accesses to the fifo. figure 75. 32-bit endian conversion notes: 1. during operation, the intcsr fifo endian conversion bits (d25:24) and 64-bit access bits (d31:30) should only be changed when the fifo is empty and is idle on both the add-on and pci interfaces. destination d 31-24 d 23-16 d 15-8 d 7-0 byte 3 byte 2 byte 1 byte 0 byte 3 byte 2 byte 1 byte 0 d 31-24 d 23-16 d 15-8 d 7-0 source destination d 31-24 d 23-16 d 15-8 d 7-0 byte 3 byte 2 byte 1 byte 0 byte 3 byte 2 byte 1 byte 0 d 31-24 d 23-16 d 15-8 d 7-0 source s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 126 data sheet 64-bit endian conversion because the s5335 interfaces to a 32-bit pci bus, special operation is required to handle 64-bit data endian conversion. figure 76 shows 64-bit endian conversion. the s5335 must know whether the lower 32-bits enter the fifo first or the upper 32-bits enter the fifo first. intcsr d3 1:30 identify which method is used by the application. these bits toggle after each 32-bit operation to indicate if half or all of a 64-bit data operation has been completed. the initial state of these bits establishes the loading and emptying order for 64-bit data during operation. figure 76. 64-bit endian conversion destination d 31-24 d 23-16 d 15-8 d 7-0 byte 7 byte 6 byte 5 byte 4 byte 3 byte 2 byte 1 byte 0 d 31-24 d 23-16 d 15-8 d 7-0 source byte 7 byte 6 byte 5 byte 4 byte 3 byte 2 byte 1 byte 0 slr slr slr slr read order: bytes 3-0 first or bytes 7-4 first see text load order: bytes 3-0 first or, bytes 7-4 first see text s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 127 data sheet add-on fifo status indicators the add-on interface implements fifo status pins to indicate the full and empty conditions of the pci to add-on and add-on to pci fifos. these may be used by the add-on to allow data transfers between the fifo and memory, a peripheral, or even a cas- caded external fifo. the rdempty and wrfull status outputs are always available to the add-on. additional status signals are multiplexed with the byte- wide, non-volatile memory in terface pins. if the s5335 is configured for add-on in itiated bus mastering, these status signals also become available to the add-on. fifo status is also indicated by bits in the add-on general control/status and bus master control/status registers. the table below lists all fifo status outputs and their functions. 1. these signals are only available when a serial non-volatile mem- ory is used and the device is configured for add-on initiated bus mastering. add-on fifo control signals the add-on interface implements fifo control pins to manipulate the s5335 fifos. these may be used by add-on to control data transfer between the fifo and memory, a peripheral, or even a cascaded external fifo. the rdfifo# and wrfifo# inputs are always available. these pins allow direct access to the fifo without generating a standard add-on register access using rd#, wr#, select#, address pins and the byte enables. additional control signals are multiplexed with the byte-wide, non-volatile memory interface pins. if a serial non-volatile memory is used and the s5335 is configured for add-on initia ted bus mastering, these control signals also become available. for pci initi- ated bus mastering, amren, amwen, frc#, and fwc# functionality is always available through bits in the bus master control/status and add-on general control/status registers. th e fifo control inputs are listed below. 1. these signals are only available when a serial non-volatile mem- ory is used and the s5335 is configured for add-on initiated bus mastering. pci bus mastering with the fifo the s5335 may initiate pci bus cycles through the fifo interface. the s5335 allows blocks of data to be transferred to and from the add-on by specifying a source/destination address on the pci bus and a transfer byte count. this dma capability allows data to be transferred across the pci bus without host cpu intervention. initiating a bus master transfer requires programming the appropriate address registers and transfer byte counts. this can be done from either the pci interface or the add-on interface. initiating bus master transfers from the add-on is advantageous because the host cpu does not have to intervene for the s5335 to become a pci initiator. at the end of a transfer the s5335 may generate an interrupt to either the pci bus (for pci initiated transfers) or add-on interface (for add-on initia ted transfers). add-on initiated bus mastering if bit 7 in location 45h of an external serial non-volatile memory is zero, the master read address register (mrar), master write address register (mwar), master read transfer count (mrtc), and master write transfer count (mwtc) are accessible only from the add-on interface. add-on initiated bus mas- tering is not possible when a byte-wide boot device is used due to shared device pins. when configured for add-on initiated bus mastering, the s5335 transfers data until the transfer count reaches zero, or it may be configured to ignore the transfer count. signal function rdempty indicates empty condition of the pci to add-on fifo wrfull indicates full condition of the add-on to pci fifo frf indicates full condition of the pci to add- on fifo 1 fwe indicates the empty condition of the add- on to pci fifo 1 signal function rdfifo# reads data from the pci to add-on fifo wrfifo# writes data into the add-on to pci fifo frc# reset pci to add-on fifo pointers and status indicators 1 fwc# reset add-on to pci fifo pointers and status indicators 1 amren enable bus mastering for add-on initiated pci reads 1 amwen enable bus mastering for add-on initiated pci writes 1 s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 128 data sheet for bus master transfers initiated by the add-on inter- face, some applications may not know the size of the data block to be transferred. to avoid constantly updating the transfer count register, the transfer count may be disabled. bit 28 in the add-on general con- trol/status register (agcsts) performs this function. disabling the transfer count also disables the interrupt capabilities. regardless of whether add-on transfer count is enabled or disabled, the add-on master read enable (amren) and add-on master write enable (amwen) inputs control when the s5335 asserts or deasserts its request to the pci bus. when add-on transfer count is enabled, the s5335 will only request the bus when both the transfer count (read or write) is not zero and the appropriate enable line (amren or amwen) is active. for add-on initiated bus master- ing, amwen and amren override the read and write bus mastering enable bits in the bus master control/ status register (mcsr). pci initiated bus mastering if bit 7 in location 45h of the external non-volatile mem- ory is one, the master read address register (mrar), master write address register (mwar), master read transfer count (mrtc), and master write transfer count (mwt c) are accessible only from the pci bus interface. in this configuration, the s5335 transfers data until the transfer count reaches zero. the transfer count cannot be disabled for pci initiated bus mastering. if no external nv memory boot device is used, the s5335 def aults to pci initiated bus mastering. address and transfer count registers the s5335 has two sets of registers used for bus mas- ter transfers. there are two operation registers for bus master read operations and two operation registers for bus master write operations. one operation register is for the transfer address (mwar and mrar). the other operation register is for the transfer byte count (mwtc and mrtc). the address registers are written with the first address of the transfer before bus mastering is enabled. once a transfer begins, this register is automatically updated to reflect the address of the current transfer. if a pci target disconnects from an s5335 initiated cycle, the transfer is retried starting from the current address in the register. if bus grant (gnt#) is removed or bus mastering is disabled (using amren or amwen), the value in the address register reflects the next address to be accessed. transfers must begin on dword boundaries. the transfer count registers contain the number of bytes to be transferred. the transfer count may be written before or after bus mastering is enabled. if bus mastering is enabled, no transfer occurs until the transfer count is programmed with a non-zero value. once a transfer begins, this register is automatically updated to reflect the number of bytes remaining to be transferred. if the transfer count registers are disabled (for add-on initiated bus mastering), transfers begin as soon as bus mastering is enabled. although transfers must begin on dword bound- aries, transfer counts do not have to be multiples of four bytes. for example, if the write transfer count (mwtc) register is programmed with a value of 10 (decimal), the s5335 performs two dword writes and a third write with only be0# and be1# asserted. bus mastering fifo management schemes the s5335 provides flexibilit y in how the fifo is man- aged for bus mastering. the fifo management scheme determines when the s5335 requests the bus to initiate pci bus cycles. the management scheme is configurable for the pci to add-on and add-on to pci fifo (and may be different for each). bus mastering must be enabled for the management scheme to apply (via the enable bits or amren/amwen). for the pci to add-on fifo, there are two manage- ment options. the pci to add-on fifo management option is programmed through the bus master control/ status register (mcsr). the fifo can be pro- grammed to request the bus when any dword location is empty or only when four or more locations are empty. after the s5335 is granted control of the pci bus, the management scheme does not apply. the device continues to read as long as there is an open fifo location. when the pci to add-on fifo is full or bus mastering is di sabled, the pci bus request is removed by the s5335. for the add-on to pci fifo, there are two manage- ment options. the add-on to pci fifo management option is programmed through the bus master control/ status register (mcsr). the fifo can be pro- grammed to request the bus when any dword location is full or only when four or more locations are full. after the s5335 is granted control of the pci bus, the management scheme does not apply. the device continues to write as long as there is data in the fifo. when the add-on to pci fifo is empty or bus mas- tering is disabled, the pci bus request is removed by the s5335. there are two special cases for the add-on to pci fifo management scheme. the first case is when the fifo is programmed to request the pci bus only when four or more locations are full, but the transfer count is less than 16 bytes. in this situation, the fifo ignores s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 129 data sheet the management scheme and finishes transferring the data. the second case is when the s5335 is config- ured for add-on initiated bus mastering with transfer counts disabled. in this si tuation, the fifo manage- ment scheme must be set to request the pci bus when one or more locations are full. amren and amwen may be used to implement a specific fifo management scheme. fifo bus master cycle priority in many applications, the fifo is used as a pci initia- tor performing both pci reads and writes. this requires a priority scheme be implemented. what hap- pens if the fifo condition for initiating a pci read and a pci write are both met? bits d12 and d8 in the bus master control/status register (mcsr) control the read and write cycle pri- ority, respectively. if these bits are both set or both clear, priority alternates, beginning with a read cycle. if the read priority is set and the write priority is clear, read cycles take priority. if the write priority is set and the read priority is clear, write cycles take priority. pri- ority arbitration is only done when neither fifo has control of the pci bus (the pci to add-on fifo would never interrupt an add-on to pci fifo transfer). fifo generated bus master interrupts interrupts may be generated under certain conditions from the fifo. if pci initiated bus mastering is used, inta# is generated to the pci interface. if add-on ini- tiated bus mastering is used, irq# is generated to the add-on interface. interrupts may be disabled. fifo interrupts may be generated from one or more of the following during bus mastering: read transfer count reaches zero, write transfer count reaches zero, or an error occurs during bus mastering. error conditions include a target or master abort on the pci bus. inter- rupts on pci error conditions are only enabled if one or both of the transfer count interrupts are enabled. the add-on interrupt contro l/status register (aint) or the interrupt control status register (intcsr) indi- cates the interrupt source. the interrupt service routine may read these registers to determine what action is required. as mail boxes are also capable of generating interrupts, this must also be considered in the service routine. interrupts are also cleared through these registers. bus interface the s5335 fifo may be accessed from the add-on interface or the pci interface. add-on fifo control and status signals allow a simple interface to the fifo with either an add-on cpu or programmable logic. the following section describes the pci and add-on interface behavior and hardware interface. fifo pci interface (target mode) the s5335 fifo may act as a standard pci target. fifo empty/full status may be determined by the pci initiator by reading the stat us bits in the pci bus mas- ter control/status register (mcsr). the fifo occupies a single 32-bit register location within the pci operation registers. a pci initiator may not perform burst accesses to a fifo as it is a single address. each data phase of a burst causes the pci initiator to incremen t its address counter (even though only the first addres s is driven at the beginning of the burst). the initiator keeps track of the current address in case a disconnect occurs. this allows the initiator to continue the burst from where the discon- nect occurred. if the s5335 fifo initiated a disconnect during a pci burst to the fifo register, the burst would be resumed at an address other than the fifo loca- tion (because the initiator address counter has incremented). the s5335 always signals a disconnect if a burst to any pci operation register is attempted. because the pci to add-on fifo and the add-on to pci fifo occupy a single location within the pci and add-on operation registers, which fifo is accessed is determined by whether the access is a read or write. this means that once data is written into the fifo, the value written cannot be read back. for pci reads from the a dd-on to pci fifo, the s5335 asserts trdy# and completes the pci cycle (figure 77). if the pci bus attempts to read an empty fifo, the s5335 immediately issues a disconnect with retry (figure 78). the add-on to pci fifo status indi- cators change one pci clock after a pci read. for pci writes to the pci to add-on, the s5335 asserts trdy# and completes the pci cycle (figure 79). if the pci bus attempts to write a full fifo, the s5335 immediately issues a disconnect with retry (fig- ure 80). the pci to add-on fifo status indicators change one pci clock after a pci write. s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 130 data sheet fifo pci interface (initiator mode) the s5335 can act as an init iator on the pci bus. this allows the device to gain control of the pci bus to transfer data to or from the fifo. internal address and transfer count registers control the number of pci transfers and the locations of the transfers. the follow- ing paragraphs assume the proper registers and bits are programmed to enable bus mastering. pci read and write transfers from the s5335 are very similar. the fifo management scheme determines when the s5335 asserts its pci bus request (req#). when bus grant (gnt#) is returned, the device begins running pci cycles. once the s5335 controls the bus, the fifo management scheme is not important. it only determines when pci bus contro l is initially requested. pci bus reads and writes are always performed as bursts by the s5335, if possible. figure 77. pci read from a full s5335 fifo figure 78. pci read from an em pty s5335 fifo (target disconnect) pci_clk pci signals add-on signals frame# ad[31:0] irdy# trdy# devsel# stop# wrfull fwe addr data pci_clk pci signals add-on signals frame# ad[31:0] irdy# trdy# devsel# stop# wrfull fwe addr data target disconnect with retry s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 131 data sheet figure 79. pci write to an empty s5335 fifo figure 80. pci write to a full s5335 fifo (target disconnect) pci_clk pci signals add-on signals frame# ad[31:0] irdy# trdy# devsel# stop# rdempty frf addr data pci_clk pci signals add-on signals frame# ad[31:0] irdy# trdy# devsel# stop# rdempty frf addr data target disconnect with retry s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 132 data sheet fifo pci bus master reads for pci read transfers (f illing the pci to add-on fifo), read cycles are perfo rmed until one of the fol- lowing occurs: - bus master read transfer count register (mrtc), if used, reaches zero - the pci to add-on fifo is full - gnt# is removed by the pci bus arbiter - amren is deasserted if the transfer count is not zero, gnt# remains asserted, and amren is asserted, the fifo continues to read data from the pci bus until there are no empty locations in the pci to a dd-on fifo. if the add-on can empty the fifo as quickly as it can be filled from the pci bus, very long bursts are possible. the s5335 deasserts req# when it comp letes the access to fill the last location in the fifo. once req# is deas- serted, it will not be reasserted until the fifo management condition is met. fifo pci bus master writes for pci write transfers (emptying the add-on to pci fifo), write cycles are perfo rmed until one of the fol- lowing occurs: - bus master write transfer count register (mwtc), if used, reaches zero - the add-on to pc i fifo is empty - gnt# is removed by the pci bus arbiter - amwen is deasserted if the transfer count is not zero, gnt# remains asserted, and amwen is asserted, the fifo contin- ues to write data to the pci bus until there are is no data in the add-on to pci fifo. if the add-on can fill the fifo as quickly as it can be emptied to the pci bus, very long bursts are possible. the s5335 deas- serts req# when it comple tes the access to transfer the last data in the fifo. once req# is deasserted, it will not be reasserted until the fifo management con- dition is met. add-on bus interface the fifo register may be accessed in two ways from the add-on interface. it can be accessed through nor- mal register accesses or directly with the rdfifo# and wrfifo# inputs. in addition, the fifo register can also be accessed syn chronous to bpclk. the add-on interface also supports datapaths which are not 32-bits. the method used to access the fifo from the add-on interface is independent of whether the fifo is a pci target or a pci initiator. add-on fifo register accesses the fifo may be accessed from the add-on interface through the add-on fifo port register (afifo) read or write. this is offset 20h in the add-on operation registers. this register is accessed synchronous to bpclk. to access the fifo as a normal add-on operation register, adr[6:2], be[3:0]#, select#, and rd# or wr# are required. figure 81 shows a synchronous fifo register burst access. select# must meet setup and hold times relative to the rising edge of bpclk. rd# and select# both asserted enables the dq outputs, and the first data location (data 0) in the fifo is driven on to the bus. the fifo address and the byte enables must be valid before valid data is driven onto the dq bus. data 0 remains valid until the next rising edge of bpclk. the rising edge of bpclk causes the fifo pointer to advance to the next location (data 1). the next rising edge of bpclk also advances the fifo pointer to the next location (data 2). the status outputs reflect the fifo condition after it advances, and are updated off of the rising edge of bpclk. when rd# or select# is deasserted, the dq bus floats. the next time a valid fifo access occurs and rd# and select# are asserted, data 2 is presented on the dq bus (as there was no bpclk edge to advance the fifo). add-on fifo direct access mode instead of generating an address, byte enables, select# and a rd# or wr# strobe for every fifo access, the s5335 allows a simple, direct access mode. using rdfifo# and wrfifo# is functionally identical to performing a standard afifo port register access, but requires less lo gic to implement. accesses to the fifo register using the direct access signals are always 32-bits wide. the only exception to this is when the mode pin is configured for 16-bit operation. in this situation, all accesses are 16-bits wide. the rd# and wr# inputs must be inactive when rdfifo# or wrfifo# is active. the adr[6:2] and be[3:0]# inputs are ignored. rdfifo# and wrfifo# act as enables with bpclk acting as the clock. a synchronous inter- face allows higher data rates. figure 82 shows a synchronous fifo register direct burst access using rdfifo#. rdfifo# acts as an enable and the first data location (data 0) in the fifo is driven on to the bus when rdfifo# is asserted. data 0 remains valid until the next rising edge of bpclk. the rising edge of bpclk causes the fifo pointer to advance to the next location (data 1). the next rising edge of bpclk advances the fifo pointer to the next location (data 2). the status outputs reflect s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 133 data sheet the fifo condition after it advances, and are updated off of the rising edge of bpclk. when rdfifo# is deasserted, the dq bus floats. the next time rdfifo# is asserted, data 2 is presented on the dq bus (as there was no bpclk edge to advance the fifo). a synchronous fifo interface has the advantage of allowing data to be accessed more quickly (in bursts) by the add-on. as a target, if a full s5335 fifo is writ- ten (or an empty fifo is read) by a pci initiator, the s5335 requests a retry. the faster the add-on inter- face can empty (or fill) the fifo, the less often retries occur. with the s5335 as a pc i initiator, a similar situ- ation occurs. not emptying or filling the fifo quickly enough results in the s5335 giving up control of the pci bus. higher pci bus data transfer rates are possi- ble through the fifo with a synchronous interface. figure 81. synchronous fifo regi ster burst read access example be[3:0]# bpclk adr[6:2] dq[31:0] select# rd# rdempty valid byte enables fifo pointer advances valid address data 1 data 2 data 0 new status new status status before read s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 134 data sheet additional status/control signals for add-on initi- ated bus mastering if a serial non-volatile memory is used to configure the s5335, and the device is configured for add-on initi- ated bus mastering, two additional fifo status signals and four additional control signals are available to the add-on interface. the frf and fwe outputs provide additional fifo status information. inputs frc#, fwc#, amren, and amwen provide additional fifo control. applications may use these signals to monitor/ control fifo flags and pci bus requests. these new signals are some of the lines that were used for byte- wide nvram interface, but now are reconfigured. the reconfigured lines are as follows: outputs: e_addr (15) frf fifo read full: indicates that the pci to add-on fifo is full. e_addr (14) fwe fifo write empty: indicates the last add-on to pci fifo. data has transferred to a final buffer and is queued for transfer, fifo is empty. inputs: eq (7) amwen add-on bus mastering writ e enable: this input is driven high to enable bus master writes. eq (6) amren add-on bus mastering read enable: this input is driven high to enable bus master reads. eq (5) frc# fifo read clear: this line is driven low to clear the pci to add-on fifo. eq (4) fwc# fifo write clear: this line is driven low to clear the add-on to pci fifo. frf (pci to add-on fifo full) and fwe (add-on to pci fifo empty) supplement the rdempty and wrfull status indicators. these additional status outputs provide additional fifo status information for add-on fifo control logic. figure 82. synchronous fifo regist er burst rdfifo# access example bpclk dq[31:0] rdfifo# rdempty data 1 data 2 data 0 fifo pointer advances status before read new status new status s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 135 data sheet the frc# and fwc# inputs allow add-on logic to reset the pci to add-on or add-on to pci fifo flags. the fifo flags can always be reset with software through the add-on general control/status register (agcsts) or the bus master control/status register (mcsr), but these hardware inputs are useful for designs which do no implement a cpu on the add-on card. asserting the frc# in put resets the pci to add- on fifo. asserting the fwc# input re-sets the add- on to pci fifo. the amren and amwen inputs allow add-on logic to individually enable and disable bus mastering for the pci to add-on and add-on to pci fifo. these inputs override the bus master control/status register (mcsr) bus master enable bits. the s5335 may re- quest the pci bus for the pci to add-on fifo when amren is asserted and may request the pci bus for the add-on to pci fifo w hen amwen is asserted. if amren or amwen is deasserted, the s5335 removes its pci bus request and gives up control of the bus. amren and amwen are useful for add-ons with external fifos cascaded into the s5335. for pci bus master write operations, the entire s5335 add-on to pci fifo and the external fifo may be filled before enabling bus mastering, providing a single long burst write rather than numerous short bursts. in some applications, the amount of data to be trans- ferred is not known. during read operations, the s5335, attempting to fill it s pci to add-on fifo, may access up to eight memory locations beyond what is required by the add-on before it stops. in this situa- tion, amren can be deassert ed to disable pci reads, and then frc# can be asserted to flush the unwanted data from the fifo. fifo generated add-on interrupts for add-on initiated bus mastering, the s5335 may be configured to generate interrupts to the add-on inter- face for the following situations: - read transfer count reaches zero - write transfer count reaches zero - an error occurred during the bus master transaction the interrupt is posted to the add-on interface with the irq# output. a high-to-low transition on this output indicates an interrupt condition. because there is a single interrupt output and multiple interrupt condi- tions, the add-on interrupt control/status register (aint) must be read to deter mine the interrupt source. this register is also used to clear the interrupt, return- ing irq# to its high state. if mailbox interrupts are also used, this must be consider ed in the interrupt service routine. 8-bit and 16-bit fifo add-on interfaces the s5335 fifo may also be used to transfer data between the pci bus and 8-bit or 16-bit add-on inter- faces. this can be done using fifo advance conditions or the s5335 mode input pin. the fifo may be used as an 8-bit or 16-bit wide fifo. to use the fifo as an 8-bit interface, the advance condition should be set for byte 0 (no data is transferred in the upper 3 bytes). to use the fifo as a 16-bit interface, the adv ance condition should be set for byte 1 (no data is transferred in the upper 2 bytes). this allows a simple add-on bus interface, but it has the disadvantage of not efficiently utilizing the pci bus bandwidth because the host is forced to perform 8-bit or 16-bit accesses to the fi fo on the pci bus. this is the only way to communicate with an 8-bit add-on through the fifo without addi tional logic to steer byte lanes on the add-on data bus. pass-thru mode is more suited to 8-bit add-on interfaces. implementing a 16-bit wide fifo is a reasonable solu- tion, but to avoid wasting pci bus bandwidth, the best method is to allow the pci bus and the fifo to oper- ate with 32-bit data. the s5335 can assemble or disassemble 32-bit quantities for the add-on interface. this is possible through the mode pin. when mode is low, the add-on data bus is 32-bits. when mode is high, the add-on data bus is 16-bits. when mode is configured for 16-bit operation, be3# becomes adr1. with the fifo direct access signals (rdfifo# and wrfifo#), the mode pin must reflect the actual add- on data bus width. with mode = 16-bits, the s5335 automatically takes two cons ecutive, 16-bit add-on writes to the fifo and assembles a 32-bit value. fifo reads operate in the same manner. two consecutive add-on reads empty the 32-bit fifo register. the 16- bit data bus is internally steered to the lower and upper words of the 32-bit fifo register. s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 136 data sheet one consideration needs to be taken when using the fifo direct access signals and letting the s5335 do byte lane steering internal ly. the default condition used to advance the fifo is byte 0. this must be changed to byte 2 or 3. when mode is configured for a 16-bit add-on bus, the first 16-bit cycle to the fifo always accesses the low 16-bits. if the fifo advance condition is left at byte 0, the fifo advances after the first 16-bit cycle and the data in the upper 16-bits is directed to the next fifo location, shifting the data. some applications hold the rdfifo# and wrfifo# inputs active for a synchronous interface. in 16-bit mode, designs must avoid wr iting to a full fifo. the data for the write is lost, but the internal mechanism to direct the 16-bit external data bus to the upper 16-bits of the fifo register is triggered. this creates a situa- tion where the fifo is out of step. the next 16-bit fifo write is directed to the upper 16-bits of the fifo, and the fifo advances inco rrectly. the wrfull out- put should be used to gate the wrfifo# input to avoid this situation. a si milar problem can occur if add-on logic attempts to read an empty fifo in 16-bit mode. rdempty should be used to gate the rdfifo# input to avoid problems with the fifo get- ting out of step. in 32-bit mode (mode = low), these situations do not occur. if fifo accesses are done without the direct access signals with mode configured for 16-bits (using adr, select#, etc.), external ha rdware must toggle adr1 between consecutive 16-bit bus cycles. the fifo advance condition must be set to correspond to the order the application accesses the upper and lower words in the fifo register. configuration the fifo configuration takes place during initialization and during operation. during initialization, the bus master register access rights are defined. during oper- ation, fifo advance conditions, endian conversion, and bus mastering capabilit ies are defined . the follow- ing section describes the bits and registers which are involved with controlling and monitoring fifo operation. fifo setup during initialization location 45h in an external non-volatile memory may be used to configure the s5335 fifo during initializa- tion. if no external non-vola tile memory is used, fifo operation is disabled. the value of bit 7 in location 45h determines if the address and transfer count registers used in bus mas- tering are accessible from the pci bus or from the add-on bus. once the configuration information is downloaded from non-volatile memory after reset, the bus mastering initializat ion method can not be changed. access to the bus master address and trans- fer count registers cannot be alternated between the pci bus and the add-on interface during operation. bits 6 and 5 in location 45h enable fifo register accesses using the rdfifo#, wrfifo#, rd# and wr# inputs synchronous to bpclk. for synchronous operation, rdfifo#, wrfifo#, rd# and wr# oper- ate as enables, using bpclk to clock data. fifo status and control bits the fifo status can be monitored and the fifo oper- ation controlled from the pci operation registers and/ or the add-on operation registers. the fifo register resides at offset 20h in t he pci and add-on operation registers. the bus master control/status (mcsr) pci operation register allows a pci host to monitor fifo activity and control fifo operation. reset controls allow the pci to add-on fifo and add-on to pci fifo flags to be reset (individually). status bits indicate if the pci to add-on fifo is empty, has four or more open spaces, or is full. status bits also indicate if the add-on to pci fifo is empty, has four or more full locations or is full. finally, fifo pci bus mastering is monitored/con- trolled though this register. location 45h configuration bits bit 7 bus master register access 0 address and transfer count registers only accessi- ble from the add-on interface 1 address and transfer count registers only accessi- ble from the pci in terface (default) bit 6 rdfifo#, rd# operation 0 enable - rdfifo# and rd# functions. 1 not allowed. must be 0. bit 5 wrfifo#, wr# operation 0 enable - wrfifo# and wr# functions. 1 not allowed. must be 0. bit 0 target latency timer enable 0 disable pci latency timer time out - will not dis- connect with retry if cannot issue trdy in speci- fied time 1 enable pci latency timer time out - will be pci 2.1 compliant s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 137 data sheet the add-on general control/status (agcsts) add- on operation register allows an add-on cpu to mon- itor fifo activity and control fifo operation. reset controls allow the pci to ad d-on fifo and add-on to pci fifo flags to be reset (individually). status bits indicate if the pci to add-on fifo is empty, has four or more open spaces, or is full. status bits also indi- cate if the add-on to pci is empty, has four or more full spaces or is full. fifo bus mastering status may be monitored through this register, but all bus master configuration is through the mcsr pci operation register. pci initiated fifo bus mastering setup for pci initiated bus mastering, the pci host sets up the s5335 to perform bus master transfers. the follow- ing tasks must be completed to setup fifo bus mastering: 1. define interrupt capabilit ies. the pci to add-on and/or add-on to pci fifo can generate a pci interrupt to the host when the transfer count reaches zero. 2. reset fifo flags. this may not be necessary, but if the state of the fifo flags is not known, they should be initialized. 3. define fifo management scheme. these bits define what fifo condition must exist for the pci bus request (req#) to be asserted by the s5335. 4. define pci to add-on and add-on to pci fifo priority. these bits determine which fifo has pri- ority if both meet the defined condition to request the pci bus. if these bits are the same, priority alternates, with read accesses occurring first. 5. define transfer source/destination address. these registers are written with the first address that is to be accessed by the s5335. these address registers are updated after each access to indicate the next address to be accessed. transfers must start on dword boundaries. 6. define transfer byte counts. these registers are written with the number of bytes to be transferred. the transfer count does not have to be a multiple of four bytes. these registers are updated after each transfer to reflect the number of bytes remaining to be transferred. intcsr bit 15 enable interrupt on read transfer count equal zero intcsr bit 14 enable interrupt on write transfer count equal zero mcsr bit 26 reset add-on to pci fifo flags mcsr bit 25 reset pci to add-on fifo flags mcsr bit 13 pci to add-on fifo management scheme mcsr bit 9 add-on to pci fifo management scheme mcsr bit 12 read vs. write priority mcsr bit 8 write vs. read priority mwar all bus master write address mrar all bus master read address mwtc all write transfer byte count mrtc all read transfer byte count s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 138 data sheet 7. enable bus mastering. once steps 1-6 are com- pleted, the fifo may operate as a pci bus master. read and write bus master operation may be independently enabled or disabled. the order of the tasks listed above is not particularly important. it is recommended that bus mastering be enabled as the last step. some applications may choose to leave bus mastering enabled and start transfers by writing a non-zero value to the transfer count registers. this also works, provided the entire transfer count is written in a single access. as a num- ber of the configuration bits and the two enable bits are all in the mcsr register , it may be most efficient for the fifo configuration bits to be set with the same register access that enables bus mastering. if interrupts are enabled, a host interrupt service rou- tine is also required. the service routine determines the source of the interrupt and resets the interrupt. as mailbox registers may also be configured to generate interrupts, the exact source of the interrupt is indicated in the pci interrupt control/status register (intcsr). typically, the interrupt servic e routine is used to setup the next transfer by writing new addresses and trans- fer counts, but some applications may also require other actions. if read transfer or write transfer com- plete interrupts are enabled, master and target abort interrupts are automatically enabled. these indicate a transfer error has occurred. writing a one to these bits clears the corresponding interrupt. add-on initiated fifo bus mastering setup for add- on initiated bus mastering, the add-on sets up the s5335 to perform bus master transfers. the following tasks must be completed to setup fifo bus mastering: 1. define transfer count ab ilities. for add-on initi- ated bus mastering, transfer counts may be either enabled or disabled. transfer counts for read and write operations cannot be individually enabled. 2. define interrup t capabilities. t he pci to add-on and/or add-on to pci fifo can generate an interrupt to the add-on when the transfer count reaches zero (if transfer counts are enabled). 3. reset fifo flags. this may not be necessary, but if the state of the fifo flags is not known, they should be initialized. 4. define fifo management scheme. these bits define what fifo condition must exist for the pci bus request (req#) to be asserted by the s5335. this must be programmed through the pci interface. mcsr bit 14 enable pci to add-on fifo bus mas- tering mcsr bit 10 enable add-on to pci fifo bus mas- tering intcsr bit 21 target abort caused interrupt intcsr bit 20 master abort caused interrupt intcsr bit 19 read transfer complete caused inter- rupt intcsr bit 18 write transfer complete caused inter- rupt agcsts bit 28 enable transfer count for read and write bus master transfers aint bit 15 enable interrupt on read transfer count equal zero aint bit 14 enable interrupt on write transfer count equal zero agcsts bit 25 reset add-on to pci fifo flags agcsts bit 26 reset pci to add-on fifo flags mcsr bit 13 pci to add-on fifo management scheme mcsr bit 9 add-on to pci fifo management scheme s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 139 data sheet 5. define pci to add-on an d add-on to pci fifo priority. these bits determine which fifo has pri- ority if both meet the defined condition to request the pci bus. if these bits are the same, priority alternates, with read ac cesses occurring first. this must be programmed through the pci interface. 6. define transfer source/destination address. these registers are writt en with the first address that is to be accessed by the s5335. these address registers are updated after each access to indicate the next address to be accessed. transfers must start on dword boundaries. mwar all bus mast er write address mrar all bus master read address 7. define transfer byte counts. these registers are written with the number of bytes to be transferred. the transfer count does not have to be a multiple of four bytes. these registers are updated after each transfer to reflect the number of bytes remaining to be transferred. if transfer counts are disabled, these registers do not need to be programmed. 8. enable bus mastering. once steps 1-7 are com- pleted, the fifo may operate as a pci bus master. read and write bus master operation may be independently enabled or disabled. the amren and amwen inputs control bus master enabling for add-on initiated bus mastering. the mcsr bus master enable bits are ignored for add-on initiated bus mastering. it is recommended that bus mastering be enabled as the last step. some applications may choose to leave bus mastering enabled (amren and amwen asserted) and start transfers by writing a non-zero value to the transfer count registers (if they are enabled). if interrupts are enabled, an add-on cpu interrupt service routine is also required. the service routine determines the source of the interrupt and resets the interrupt. as mailbox registers may also be configured to generate interrupts, the exact source of the interrupt is indicated in the add-on interrupt control register (aint). typically, the interrupt service routine is used to setup the next transfer by writing new addresses and transfer counts (if enabled), but some applications may also require other actions. if read transfer or write transfer complete interrupts are enabled, the master/ target abort interrupt is automatically enabled. these indicate a transfer error has occurred. writing a one to these bits clears the corresponding interrupt. mcsr bit 12 read vs. write priority mcsr bit 8 write vs. read priority mwtc all write transfer byte count mrtc all read transfer byte count aint bit 21 master/target abort caused interrupt aint bit 19 read transfer complete caused interrupt aint bit 18 write transfer complete caused interrupt s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 140 data sheet pass-thru overview the s5335 provides a simple registered access port to the pci bus. using a handshak ing protocol with add- on card logic, the pci bus directly accesses resources on the add-on. the pass-thru data transfer method is very useful for direct add-on memory access, or accessing registers within peripherals on an add-on board. pass-thru operation requires an external nv memory boot device to define and configure the s5335 pass-thru regions. the s5335 provides four user-configurable pass-thru regions. each region corresponds to a pci configura- tion base address register (badr1-4). a region represents a block of address space (the block size is user-defined). each block can be mapped into mem- ory or i/o space. memory mapped regions can request to be located below 1 mbyte (real mode address space for a pc). each regi on also has a configurable bus width for the add-on bus interface. an 8-, 16-, or 32-bit add-on interface may be selected, for use with a variety of add-on memory or peripheral devices. pass-thru features can be used only when the s5335 is a pci target. as a target, the s5335 pass-thru mode supports single data transfers as well as burst transfers. when accessed with burst transfers, the s5335 supports data transfers at the full pci band- width. the data transfer rate is only limited by the pci initiator performing the access and the speed of the add-on logic. functional description to provide the pci bus add-on with direct access to add-on resources, the s5335 has an internal pass- thru address register (apta), and a pass-thru data register (aptd). these registers are connected to both the pci bus interface and the add-on bus inter- face. this allows a pci init iator to perform pass-thru writes (data transferred from the pci bus to the add- on bus) or pass-thru reads (pci bus requests data from the add-on bus). the s5335 pass-thru interface supports both single cycle (one data phase) and burst accesses (multiple data phases). pass-thru transfers data transfers between t he pci bus and the add-on using the pass-thru interface are implemented with a handshaking scheme. if the pci bus writes to an s5335 pass-thru region, add-on logic must read the data from the s5335 and store it on the add-on. if the pci bus reads from a pass-thru region, add-on logic must write data to the s5335. some applications may require that an address be passed to the add-on for pass-thru accesses. for example, a 4 kbyte pass-thru region on the pci bus may correspond to a 4 kbyte block of sram on the add-on card. if a pci initiator accessed this region, the add-on would need to know the offset within the memory device to access. the pass-thru address register (apta) allows the add-on to access address information for the current pci cycle. when the pci bus performs burst accesses, the apta register is updated by the s5335 to reflect the address of the cur- rent data phase. for pci writes to the add-on, the s5335 transfers the data from the pci bus into the pass-thru data regis- ter (aptd). the s5335 captures the data from the pci bus when trdy# is asserted. the pci bus then becomes available for other transfers. when the pass- thru data register becomes full, the s5335 asserts the pass-thru status signals to indicate to the add-on that data is present. the add-on logic may read the data register and assert ptrdy# to indicate the current access is complete. until the current access com- pletes, the s5335 responds to further pass-thru accesses with retries. for pci reads from the add-on, the s5335 asserts the pass-thru status signals to indicate to the add-on that data is required. the add-on logic should write to the pass-thru data register and assert ptrdy# to com- plete the access. the s5335 does not assert trdy# to the pci bus until ptrdy# is asserted by add-on logic. if the add-on cannot provide data quickly enough, the s5335 signals a retry to the pci bus. this allows the pci bus to perform other tasks, rather than waiting for a slow target. s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 141 data sheet pass-thru status/control signals the s5335 pass-thru regi sters are accessed using the standard add-on register access pins. the pass- thru address register (apta) can, optionally, be accessed using a single, di rect access input, ptadr#. pass-thru cycle status indicators are provided to con- trol add-on logic based on the type of pass-thru access occurring (single cycl e, burst, etc.). the follow- ing signals are provided for pass-thru operation: pass-thru add-on data bus sizing many applications require an 8-bit or 16-bit add-on bus interface. pass-thru re gions can be configured to support bus widths other than 32-bits. each pass-thru region can be defined, during initialization, as 8, 16-, or 32-bits. all of the regions do not need to be the same. this feature allows a simple interface to 8-and 16-bit add-on devices. to support alternate add-on bus widths, the s5335 performs internal data bus steering. this allows the add-on interface to assemble and disassemble 32-bit pci data using multiple a dd-on accesses to the pass- thru data register (aptd). the add-on byte enable inputs (be[3:0]#) are used to access the individual bytes or words within aptd. bus interface the pass-thru interface on the s5335 is a pci target- only function. pass-thru op eration allows pci initia- tors to read or write resources on the add-on card. a pci initiator may access the add-on with single data phase cycles or multiple data phase bursts. the add-on interface implements pass-thru status and control signals used by logic to complete data transfers initia ted by the pci bus. the pass-thru inter- face is designed to allow add-on logic to function with- out knowledge of pci bus ac tivity. add-on logic only needs to react to the pass-thru status outputs. the s5335 pci interface independently interacts with the pci initiator to control data flow between the devices. the following sections describe the pci and add-on bus interfaces. the pci interface description provides a basic overview of how the s5335 interacts with the pci bus, and may be useful in system debugging. the add-on interface description indicates functions required by add-on logic and details the pass-thru handshaking protocol. pci bus interface the s5335 decodes all pci bus cycle addresses. if the address associated with the current cycle is to one of s5335 pass-thru regions, devsel# is asserted. if the pass-thru logic is current ly idle (not busy finishing a previous pass-thru operation), the bus cycle type is decoded and the add-on pass-thru status outputs are set to initiate a transfer on the add-on side. if the pass-thru logic is currently busy completing a previ- ous access, the s5335 signals a retry to pci initiator. the following sections describe the behavior of the pci interface for pass-thru accesses to the s5335. single cycle accesses, burst accesses, and target-ini- tiated retries are detailed. pci pass-thru single cycle accesses single cycle transfers are the simplest pci bus trans- action. single cycle transfers have an address phase and a single data phase. the pci bus transaction starts when an initiator drives address and command information onto the pci bus and asserts frame#. the initiator always deasserts frame before the last data phase. for single cycle transfers, frame# is only asserted during the address phase (indicating the first data phase is also the last). signal function ptatn# this output indica tes a pass-thru access is occurring ptburst# this output indicates the pass-thru access is a pci burst access ptnum[1:0] these outputs indicate which pass-thru region decoded the pci address ptbe[3:0]# these outputs indicate which data bytes are valid (pci writes), or requested (pci reads) ptwr this output indicates if the pass-thru access is a pci read or a write ptadr# when asserted, this input drives the pass-thru address r egister contents onto the add-on data bus ptrdy# when asserted, this input indicates the current pass-thru transfer has been com- pleted by the add-on bpclk buffered pci bus clock output (to syn- chronize pass-thru data register accesses) s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 142 data sheet when the s5335 sees fram e# asserted, it samples the address and command information to determine if the bus transaction is intended for it. if the address is within one of the defined pass-thru regions, the s5335 accepts the transfer (assert devsel#), and stores the pci address in the pass-thru address reg- ister (apta). for pass-thru writes, the s5335 responds immedi- ately (asserting trdy#) and transfers the data from the pci bus into the pass-th ru data register (aptd). the s5335 then indicates to the add-on interface that a pass-thru write is taking place and waits for add-on logic to read the aptd register and complete the transfer (assert ptrdy#). once the s5335 has cap- tured the data from the pci bus, the transfer is finished from the pci bus perspective, and the pci bus becomes available for other transfers. for pass-thru reads, the s5335 indicates to the add- on interface that a pass-thru read is taking place and waits for add-on logic to write the pass-thru data register and complete the transfer (assert ptrdy#). the s5335 completes the cycle when data is written into the data register. if the add-on cannot complete the write quickly enough, the s5335 requests a retry from the initiator. see target-requested disconnect information. pci pass-thru burst accesses for pci pass-thru burst accesses, the s5335 cap- tures the pci address and determines if it falls into one of the defined pass-thru r egions. accesses that fall into a pass-thru region are accepted by asserting devsel#. the s5335 monitors frame# and irdy# on the pci bus to identify burst accesses. if the pci initiator is performing a burst access, the pass-thru status indicators notify add-on logic. for pass-thru burst writes, the s5335 responds immediately (asserting trdy#). the s5335 transfers the first data phase of the burst into the pass-thru data register (aptd), and stores the pci address in the pass-thru address register (apta). the add-on interface completes the transfer and asserts ptrdy#. every time ptrdy# is asserted by the add-on, the s5335 begins the next data phase. the next data phase is latched into the data register. for burst accesses, apta is automatically incremented by the s5335 for each data phase. for pass-thru burst reads, the s5335 claims the pci cycle (asserting devsel#). the request for data is passed on to add-on logic and the pci address is stored in the apta register. the add-on interface completes the transfer and asserts ptrdy#. the s5335 then drives the requested data on the pci bus and asserts trdy# to begin the next data phase. the apta register is automat ically incremented by the s5335 for each data phase. pci retry conditions in some applications, add-on logic may not be able to respond to pass-thru accesse s quickly. in this situa- tion, the s5335 disconnects from the pci bus, signaling a retry. this indica tes that the initiator should try the access again at a later time. this allows other pci cycles to be run while the logic on the slow target completes the pass-thru access. ideally, when the ini- tiator retries the access, the target has completed the access and can respond to the initiator. with many devices, particularly memories, the first access takes longer than subsequent accesses (assuming they are sequential and not random). for this reason, the pci specification allows 16 clocks to respond to the first data phase of a pci cycle and 8 clocks for subsequent data phas es (in the case of a burst) before a retry must be requested by the s5335. the s5335 also requests a retry if an initiator attempts to burst past the end of a pass-thru region. the s5335 updates the pass-thru address register (apta) for each data phase during bursts, and if the updated address is not within the current pass-thru region, a retry is requested. for example, a pci system may map a 512 byte pass- thru memory region to 0dc000h to 0dc1ffh. a pci initiator attempts a four dw ord burst with a starting address of 0dc1f8h. the first and second data phases complete (filling the dwords at 0dc1f8h and 0dc1fch), but the third data phase causes the s5335 to request a retry. this forces the initiator to present the address 0dc200h on the pci bus. if this address is part of another s5335 pass-thru region, the device accepts the access. pci write retries when the s5335 requests a retry for a pci pass-thru write, it indicates that the add-on is still completing a previous pass-thru write access. the pass-thru address and data register contents (apta and aptd) are still required for the previous pass-thru operation and cannot be updated by the pci interface until the access completes (the add-on asserts ptrdy#). s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 143 data sheet when the add-on is busy completing a pass-thru write, the s5335 requests an immediate retry for all pass-thru region accesses, allowing the pci bus to perform other operations. pci operation registers may be accessed while the ad d-on is still completing a pass-thru access. only pa ss-thru region accesses receive retry requests. pci read retries when the s5335 requests a retry for a pci pass-thru read, it indicates that the add-on could not complete the read in the required time. the pass-thru data can- not be read by the pci interface until the add-on asserts ptrdy#, indicating the access is complete. if the retry occurs after the add-on has completed the pass-thru operation by writing the appropriate data into the pass-thru data register and asserting ptrdy#, the s5335 asserts devsel# and trdy# to complete the pci read. if the add-on still has not com- pleted the pass-thru read, the s5335 waits for the required 16 clocks. if th e add-on completes the access during this time, trdy# is asserted and the access is finished. if the a dd-on cannot complete the access within 16 clocks, another retry is requested. when the add-on is busy completing a pass-thru read, the s5335 requests an immediate retry for all pass-thru region accesses, except the region cur- rently completing the previo us access. this allows the pci bus to perform other ope rations. the next access to the pass-thru region which initiated the retry must be to the same address which caused the retry. another initiator accessing the same pass-thru region causes the s5335 to respond with the original initia- tor?s data (for reads). s5335 pci operation registers may be accessed while the add- on is still completing a pass-thru access. only other pass-thru region accesses receive retry requests. add-on bus interface the pass-thru address and data registers can be accessed as add-on operation registers. the inter- face to the pass-thru regi sters is described in. the pass-thru data register is updated on the rising edge of bpclk. for this reason, all pass-thru inputs must be synchronous to bpclk. in the following sections the add-on pass-thru interface is described for pass- thru single cycle accesses, burst accesses, target- requested retries, and when using 8-bit and 16-bit add-on data buses. single cycle pass-thru writes a single cycle pass-thru write operation occurs when a pci initiator writes a si ngle value to a pass-thru region. pci single cycle tr ansfers consists of an address phase and one data phase. during the address phase of the pci transfer, the s5335 stores the pci address into the pass-thru address register (apta). if the s5335 determines that the address is within one of its defined pass-thru regions, it captures the pci data into the pass-thru data register (aptd). figure 83 shows a single cycle pass-thru write access (add-on read). the add-on must read the data stored in the aptd register and transfer it to its destination. note: rd# ma y be asserted for multiple clocks to allow interfacing with slow add-on devices. data remains valid unt il ptrdy# is asserted. s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 144 data sheet figure 83. single cycle pass-thru write note: for all add-on accesses using ptadr for address data when in 16 bit mode, adr[1] must be held low to get the low address word. bpclk 0 1 2 3 4 5 0h 1 2ch 0h pta tn# ptburst# ptnum[1:0] ptwr ptbe[3:0]# select# adr[6:2] be[3:0]# rd# dq[31:0] ptrdy # pt da ta pci write cycle completed s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 145 data sheet figure 84 shows a single cycle pass-thru write using the pass-thru address information. this provides pci cycle address information to select a specific address location within an add-on memory or peripheral. add- on logic must latch the address for use during the data transfer. typically, the entire 32-bit address is not required. the add-on may implement a scheme where only the required number of address bits are latched. it may also be usef ul to use the pass-thru region identifiers, ptnum[1:0] as address lines. for example, pass-thru region 1 might be a 64k block of sram for data, while pass-thru region 2 might be 64k of sram for code storage (down-loaded from the host during initialization). using ptnum0 as address line a16 allows two unique ad d-on memory regions to be defined. figure 84. single cycle pass-thru write with ptadr# clock 0: the pci bus cycle address information is stor ed in the s5335 pass-th ru address register. clock 1: the pci address is recognized as a write to pass-thru regi on 1. the pci data is stored in the s5335 pass-thru data register. ptatn# is asserted to i ndicate a pass-thru access is occurring. clock 2: pass-thru status signals indicate what action is require d by add-on logic. pass-thru status outputs are valid when ptatn# is active and are sampled by the add-on at the rising edge of clock 2. ptburst# deasserted. the access has a single data phase. ptnum[1:0] 01. indicates the pci a ccess is to pass-thru region 1. ptwr asserted. the pass-thru access is a write. ptbe[3:0]# 0h. indicates the pass-thru access is 32-bits. select#, address and byte enable inputs are driven to read the pass-thru data register at offset 2ch. dq[31:0] are driven after rd# and select# are asserted. clock 3: if ptrdy# is asserted at the rising edge of clock 3, ptatn# is immediately deasserted and the pass-thru access is completed at clock 4. clock 4: if add-on logic requires mo re time to read the pass-thru data re gister (slower memory or peripherals), ptrdy# can be delayed, extending the cycle. with ptrdy # asserted at the rising edge of clo ck 4, ptatn# is deasserted and the pass-thru a ccess is completed at clock 5. clock 5: ptatn# and ptburst# deasserted at the rising edge of clock 5 indicates the pass -thru access is complete. the s5335 can accept new pass-thru accesses from the pci bus at clock 6. bpclk 0 1 2 3 4 5 6 0h 1 2ch 0h ptatn# pt burst # ptnum[1:0] ptwr ptbe[3:0]# select# adr[6:2] be[3:0]# rd# dq[31:0] pt rdy# ptadr# pt addr pt dat a pci write cycle completed s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 146 data sheet the add-on ptadr# input directly accesses the pass-thru address register and drives the contents onto the data bus (no bpclk rising edge is required). the byte enables, address, and select# inputs are ignored when ptadr# is asserted. rd# and wr# must not be asserted when ptadr# is asserted. clock 0: the pci bus cycle address is stored in the s5335 pass-thru address register. clock 1: the pci address is recognized as an access to pass-thru region 1. pci data is stored in the s5335 pass-thru data register. ptatn# is asserted to i ndicate a pass-thru access is occurring. clock 2: pass-thru status signals indicate what action is requir ed by add-on logic. pass-thru status outputs are valid when ptatn# is active and are sampled by the add-on at the rising edge of clock 2. ptburst# deasserted. the acce ss has a single data phase. ptnum[1:0] 01. indicates the pci a ccess is to pass-thru region 1. ptwr asserted. the pass-th ru access is a write. ptbe[3:0]# 0h. indicate the pass-thru access is 32-bits. the ptadr# input is asserted to read the pass-thru address register. the byte enable, address, and select# inputs are changed during this clock to se lect the pass-thru data register during clock cycle 3. clock 3: select#, byte enable, and the address inputs remain valid to read the pass-thru data register at offset 2ch. rd# is asserted to drive data register contents onto the dq bus. clock 4: if ptrdy# is asserted at the rising edge of clock 4, ptatn# is immediately deasserted and the pass-thru access is completed at clock 5. clock 5: if add-on logic requires mo re time to read the pass-thru data re gister (slower memory or peripherals), ptrdy# can be delayed, extendin g the cycle. ptrdy# asserted at the rising edge of clock 5 causes ptatn# to be immediately deasserted. clock 6: ptatn# and ptburst# deasserted at the rising edge of clock 6 indicates the pass -thru access is complete. the s5335 can accept new pass-thru accesses from the pci bus at clock 7. s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 147 data sheet single cycle pass-thru reads a single cycle pass-thru re ad operation occurs when a pci initiator reads a sing le value from a pass-thru region. pci single cycle tr ansfers consists of an address phase and a one data phase. during the ad- dress phase of the pci transfer, the s5335 stores the pci address into the pass-thru address register (apta). if the s5335 determi nes that the address is within one of its defined pass-thru regions, it indicates to the add-on that a write to the pass-thru data reg- ister (aptd) is required. figure 85 shows a single cycle pass-thru read access (add-on write) using ptadr#. the add-on reads data from a source on the add-on and writes it to the aptd register. pass-thru burst writes a pass-thru burst write operation occurs when a pci initiator writes mult iple values to a pass-thru region. a pci burst cycle consists of an address phase and mul- tiple data phases. during the address phase of the pci transfer, the s5335 stores the pci address into the pass-thru address register (apta). if the s5335 determines that the address is within one of its defined pass-thru regions, it captures the pci data into the pass-thru data register (aptd). after the add-on completes each read from the pass-thru data register (asserts ptrdy#), the next data phase is initiated. figure 86 shows a 6 data phase pass-thru burst write (add-on read). in this case, the add-on asserts ptadr# and then reads multiple data phases from the s5335. this works well for add-on logic which sup- ports burst cycles. if the add-on logic does not support burst accesses, ptadr# may be pulsed before each data phase. the s5335 automatically increments the address in the apta register during pci burst cycles. in this example ptrdy# is always asserted, indicating add-on logic is capable of accept- ing data at a rate of one dword per clock cycle. clock 0: pci address information is stored in the s5335 pass-thru address register. the pci cycle is recognized as an access to pass-thru region 1. ptatn# is asserted by the s5335 to indi cate a pass-thru access is occurring. clock 1: pass-thru status signals indicate what action is requir ed by add-on logic. pass-thru status outputs are valid when ptatn# is active and are sampled by the add-on at the rising edge of clock 1. ptburst# deasserted. the access has a single data p hase. ptnum[1:0] 01. indicates the pci access was to pass-thru region 1. ptwr deasserted. the pass-thru access is a read. ptbe[3:0]# 0h. indicate the pass-thru access is 32-bits. the ptadr# input is asserted to read the pass-thru ad dress register. the byte enable, address, and select# inputs are changed durin g this clock to select the pass-thru data register during clock cycle 3. clock 2: this clock is required to avoid contention on the dq bus. time must be allowed after ptadr# is deasserted for the dq outputs to float before add-on logic atte mpts to write to the pass-thru data register. clock 3: select#, byte enables, and the address inputs remain valid to write the pass-thru data register at offset 2ch. if wr# is asserted at the rising edge of clock 3, data on the dq bus is latched into aptd. if ptrdy# is asserted at the rising edge of clock 3, ptatn# is immediately deasserted and the pass-thru access is completed at clock 4. clock 4: if add-on logic requires more time to write the pass-thru data regist er (slower memory or peripherals), ptrdy# can be delayed, extending the cycle. ptrdy# asserted at t he rising edge of clock 4 causes ptatn# to be imme- diately deasserted and the pass-thru access is completed at clock 5. clock 5: ptatn# and ptburst# deasserted at the rising edge of clock 5 indicates the pass -thru access is complete. the s5335 can accept new pass-thru accesses from the pci bus at clock 6. s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 148 data sheet clock 0: pci address information is stored in the s5335 pass-thru address register. clock 1: the pci address is recognized as an acce ss to pass-thru region 1. pci data for the first data phase is stored in the s5335 pass-thru data register. ptatn# is asserted by the s5335 to indicate a pass-thru access is occur- ring. clock 2: pass-thru status signals indicate what action is requir ed by add-on logic. pass-thru status outputs are valid when ptatn# is active and are sampled by the add-on at the rising edge of clock 2. ptburst# asserted. the access has a multiple data phases. ptnum[1:0] 01. indicates the pci access was to pass-thru region 1. ptwr asserted. the pass-thru access is a write. ptbe[3:0]# 0h. indicate the pass-thru access is 32-bits. the ptadr# input is asserted to read the pass-thru address register. the byte enable, address, and select# inputs are changed during this clock to select the pass-thru data register during clock cycle 3. clock 3: select#, byte enables, and the address inputs remain driven to read the pass-thru data register at offset 2ch. rd# is asserted to drive data register contents onto the dq bus. clock 4: add-on logic uses the rising edge of clock 4 to stor e data 1 from the s5335. ptrdy# asserted at the rising edge of clock 4 completes the current data phase. data 2 is driven on the add-on bus. clock 5: add-on logic uses the rising edge of clock 5 to stor e data 2 from the s5335. ptrdy# asserted at the rising edge of clock 5 completes the current data phase. data 3 is driven on the add-on bus. clock 6: add-on logic uses the rising edge of clock 6 to stor e data 3 from the s5335. ptrdy# asserted at the rising edge of clock 6 completes the current data phase. on the pci bus, irdy# has been deasserted, causing ptatn# to be deasserted. this is how a pci initiator ad ds wait states, if it canno t provide data quickly enough. data on the add-on bus is not valid. clock 7: because ptatn# remains deasserted, add-on logic cannot st ore data at the rising edge of clock 7. ptatn# is reasserted, indicating the pci initiator is no longer adding wait states. data 4 is driven on the add-on bus. clock 8: add-on logic uses the rising edge of clock 8 to stor e data 4 from the s5335. ptrdy# asserted at the rising edge of clock 8 completes the current data phase. on the pci bus, irdy# has been deasserted again, causing ptatn# to be deasserted. data on the add-on bus is not valid. clock 9: the pci initiator is still adding wait states. add-on logic cannot store data while ptatn# is deasserted. clock 10: because ptatn# remains deasserted, add-on logic cannot read data at the rising edge of clock 10. ptatn# is reasserted, indicating the pci initiator is no longer adding wait states. data 5 is driven on the add-on bus. clock 11: add-on logic uses the rising edge of clock 11 to store data 5 from the s5335. ptrdy# asserted at the rising edge of clock 11 completes the current data phase. data 6 is driven on the add-on bus. clock 12: add-on logic uses the rising edge of clock 12 to store data 6 from the s5335. ptrdy# asserted at the rising edge of clock 12 completes the final data phase. clock 13: ptatn# and ptburst# deasserted at the rising edge of clock 13 indicates the pass- thru access is complete. the s5335 can accept new pass-thru accesses from the pci bus at clock 15. s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 149 data sheet figure 85. single cycle pass-thru read with ptadr# figure 86. pass-thru burst write bpclk 0 1 2 3 4 5 0h 1 2ch 0h pta tn# ptburst# ptnum[1:0] ptwr ptbe[3:0]# select# adr[6:2] be[3:0]# wr# dq[31:0] ptrdy # pta dr# pt a ddr pt da ta pci read cycle completed data stored in pass-thru data register 6 1 0 1 1 1 2 1 3 9 8 7 6 5 4 3 2 1 1 0 b p c l k p t a t n # p t b u r s t # p t n u m [ 1 : 0 ] p t w r p t b e [ 3 : 0 ] # 0 h d a t a 1 p t a d d r d a t a 2 d a t a 3 d a t a 4 x x x x d a t a 5 d a t a 6 x x x x x x x x 2 c h 0 h s e l e c t # a d r [ 6 : 2 ] p t r d y # p t a d r # b e [ 3 : 0 ] # r d # d q [ 3 1 : 0 ] v a l i d p c i d a t a o n d q b u s p c i b u r s t w r i t e c o m p l e t e d s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 150 data sheet figure 87 also shows a 5 data phase pass-thru burst write, but the add-on logic uses ptrdy# to control the rate at which data is transferred. in many applica- tions, add-on logic is not fa st enough to accept data at every bpclk rising edge (every 30 ns in a 33 mhz pci system). in this example, the add-on interface accepts data every other clock. in the example, rd# is asserted during the entire add-on burst, but it can be deasserted when ptrdy# is deasserted, the s5335 functions the same under both conditions. figure 87. pass-thru burst writes controlled by ptrdy# 1 0 1 1 1 2 1 3 9 8 7 6 5 4 3 2 1 0 1 0 b p c l k p t a t n # p t b u r s t # p t n u m [ 1 : 0 ] p t w r p t b e [ 3 : 0 ] # 0 h f h d a t a 1 p t a d d r d a t a 2 d a t a 3 d a t a 5 x x x x d a t a 4 2 c h 0 h s e l e c t # a d r [ 6 : 2 ] p t r d y # p t a d r # b e [ 3 : 0 ] # r d # d q [ 3 1 : 0 ] v a l i d p c i d a t a o n d q b u s p c i b u r s t w r i t e c o m p l e t e d s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 151 data sheet clock 0: pci address information is stored in the s5335 pass-thru address register. clock 1: the pci address is recognized as an access to pass-thru region 1. pci data for the first data phase is stored in the s5335 pass-thru data register. ptatn# is asse rted by the s5335 to indicate a pass-thru access is occurring. clock 2: pass-thru status signals indicate what action is requir ed by add-on logic. pass-thru status outputs are valid when ptatn# is active and are sampled by the add-on at the rising edge of clock 2. ptburst# asserted. the access has multiple data phases. ptnum[1:0] 01. indicates the pci access is to pass-thru region 1. ptwr asserted. the pass-th ru access is a write. ptbe[3:0]# 0h. indicate the pass-thru access is 32-bits. the ptadr# input is asserted to read the pass-thru address register. the byte en-able, address, and select# inputs are changed during this clock to select the pass-th ru data register during clock cycle 3. clock 3: select#, byte enable, and the address inputs remain driven to read the pass-thru data register at offset 2ch. rd# is asserted to drive data regi ster contents onto the add-on data bus. clock 4: add-on logic uses the rising edge of clock 4 to stor e data 1 from the s5335. ptrdy# asserted at the rising edge of clock 4 completes the current data ph ase. data 2 is driven on the add-on bus. clock 5: add-on logic is not fast enough to store data 2 by th e rising edge of clock 5. ptrdy# deasserted at the ris- ing edge of clock 5 extends the current data phas e and data 2 remains driven on the add-on bus. clock 6: add-on logic uses the rising edge of clock 6 to stor e data 2 from the s5335. ptrdy# asserted at the rising edge of clock 6 completes the current data ph ase. data 3 is driven on the add-on bus. clock 7: add-on logic is not fast enough to store data 3 by th e rising edge of clock 7. ptrdy# deasserted at the ris- ing edge of clock 7 extends the current data phase is and data 3 remains driven on the add-on bus. clock 8: add-on logic uses the rising edge of clock 8 to stor e data 3 from the s5335. ptrdy# asserted at the rising edge of clock 8 completes the current data phase. on the pci bus, irdy# has been deasserted, causing ptatn# to be deasserted. data on the add-on bus is not valid. clock 9: because ptatn# remains deasserted, add-on logic cannot store data at the rising edge of clock 9. ptatn# is reasserted, indicating the pci initiator is no lon ger adding wait states. data 4 is driven on the add-on bus. clock 10: add-on logic uses the rising edge of clock 10 to stor e data 4 from the s5335. ptrdy# asserted at the rising edge of clock 10 completes the current data phase. data 5 is driven on the add-on bus. ptburst# is deas- serted, indicating that on the pci bus, the burst is comple te except for the last data phase. since the data is double buffered, there may be one or two pieces of data available to the add-on when ptburst# becomes inactive. this example shows the single data available case. if another piece of data was available, then ptatn# would remain active instead of going inactive at clock 12. clock 11: add-on logic is not fast enough to store data 5 by th e rising edge of clock 11. ptrdy# deasserted at the ris- ing edge of clock 11 extends the data phase and data 5 remains driven on the add-on bus. clock 12: add-on logic uses the rising edge of clock 12 to stor e data 5 from the s5335. ptrdy# asserted at the rising edge of clock 12 completes the final data phase. clock 13: ptatn# deasserted at the rising edge of clock 13 in dicates the pass-thru access is complete. the s5335 can accept new pass-thru accesse s from the pci bus at clock 14. s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 152 data sheet pass-thru burst reads a pass-thru burst read operation occurs when a pci initiator reads multiple dwords from a pass-thru region. a burst transfer consists of a single address and a multiple data phases. during the address phase of the pci transfer, the s5335 stores the pci address into the pass-thru address register (apta). if the s5335 determines that the address is within one of its defined pass-thru regions, it indicates to the add-on that a write to the pass-thru data register (aptd) is required. figure 88 shows a 6 data phase pass-thru burst read access (add-on write) using ptadr#. figure 88. pass-thru burst read 1 0 1 1 1 2 1 3 9 8 7 6 5 4 3 2 1 1 0 b p c l k p t a t n # p t b u r s t # p t n u m [ 1 : 0 ] p t w r p t b e [ 3 : 0 ] # 0 h f h d a t a 1 d a t a 2 d a t a 4 d a t a 6 d a t a 5 2 c h 0 h s e l e c t # a d r [ 6 : 2 ] p t r d y # p t a d r # b e [ 3 : 0 ] # w r # d q [ 3 1 : 0 ] v a l i d d a t a w r i t t e n i n t o d a t a r e g i s t e r p t a d d r d a t a 3 d a t a 7 s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 153 data sheet clock 0: pci address information is stored in the s5335 pass-thru address register. the pci address is recognized as an access to pass-thru region 1. ptat n# is asserted by the s5335 to indica te a pass-thru access is occurring. ptburst# is asserted by the s5335, indicati ng the current pass-thru read is a burst. clock 1: pass-thru status signals indicate what action is requir ed by add-on logic. pass-thru status outputs are valid when ptatn# is active and are sampled by the add-on at the rising edge of clock 2. ptburst# deasserted, the s5335 does not yet recognize a pci burst. ptnum[1:0] 01. indicates the pci a ccess is to pass-thru region 1. ptwr deasserted. the pass-thru access is a read. ptbe[3:0]# 0h. indicate the pass-t hru access is 32-bits. the ptadr# input is asserted to read the pass-thru address register. the byte enable, address, and select# inputs are changed during this clock to sele ct the pass-thru data r egister during clock cycle 3. clock 2: select#, byte enables, and the address inputs remain driven to read the pass-thru data register at offset 2ch. clock 3: wr# asserted at the rising edge of clock 3 writes data 1 into the s5335. ptrdy# asserted at the rising edge of clock 3 completes the current data phase. clock 4: wr# asserted at the rising edge of clock 4 writes data 2 into the s5335. ptrdy# asserted at the rising edge of clock 4 completes the current data phase. clock 5: wr# asserted at the rising edge of clock 5 writes data 3 into the s5335. ptrdy# asserted at the rising edge of clock 5 completes the current data phase. on the pci bus, irdy# has been deasserted, causing ptatn# to be deasserted. this is how a pci initiator adds wait states, if it cannot read data quickly enough. clock 6: ptatn# remains deasserted at the rising edge of clock 6. the add-on cannot write data 4 until ptatn# is asserted. ptatn# is reassert ed during the cycle, indicating the pci in itiator is no longer adding wait states. add-on logic continues to drive data 4 on the add-on bus. clock 7: wr# asserted at the rising edge of clock 7 writes data 4 into the s5335. ptrdy# asserted at the rising edge of clock 7 completes the current data phase. on the pci bus, irdy# has been deasserted, causing ptatn# to be deasserted. the pci initiator is adding wait states. clock 8: ptatn# remains deasserted at the rising edge of clock 8. the add-on cannot write data 5 until ptatn# is asserted. add-on logic continues to drive data 5 on the add-on bus. clock 9: ptatn# remains deasserted at the rising edge of clock 9. the add-on cannot write data 5 until ptatn# is asserted. add-on logic cont inues to drive data 5 on the add-on bu s. ptatn# is reasserted during the cycle, indicating the pci initiator is done adding wait states. clock 10: wr# asserted at the rising edge of clock 10 writes data 5 into the s5335. ptrdy# asserted at the rising edge of clock 10 completes the current data phase. clock 11: wr# asserted at the rising edge of clock 11 writes da ta 6 into the s5335. ptrdy# asserted at the rising edge of clock 11 completes the final data phase. clock 12: ptburst# is deasserted at the rising edge of clock 12 indicating the pass-thru burst is complete. the s5335 can accept new pass-thru accesses from the pci bus at clock 14. any data written into the pass-thru data reg- ister is not required and is never passed to the pci interf ace (as ptrdy# is not asserted at the rising edge of clock 13). s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 154 data sheet figure 89 also shows a 5 data phase pass-thru burst read, but the add-on logic uses ptrdy# to control the rate at which data is transferred. in many applica- tions, add-on logic is not fast enough to provide data every bpclk (every 30 ns in a 33 mhz pci system). in this example, the add-on interface writes data every other clock cycle. wr# is shown asserted during the entire add-on burst, but wr# can be deasserted when ptrdy# is deasserted, the s5335 functions the same under both conditions. figure 89. pci burst read controlled by ptrdy# 1 0 1 1 1 2 1 3 9 8 7 6 5 4 3 2 1 0 1 0 b p c l k p t a t n # p t b u r s t # p t n u m [ 1 : 0 ] p t w r p t b e [ 3 : 0 ] # 0 h f h d a t a 1 p t a d d r d a t a 2 d a t a 3 d a t a 5 2 c h 0 h s e l e c t # a d r [ 6 : 2 ] p t r d y # p t a d r # b e [ 3 : 0 ] # w r # d q [ 3 1 : 0 ] v a l i d d a t a w r i t t e n i n t o d a t a r e g i s t e r d a t a 4 s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 155 data sheet clock 0: pci address information is stored in the s5335 pass-thru address register. the pci address is recognized as an access to pass-thru region 1. ptat n# is asserted by the s5335 to indica te a pass-thru access is occurring. ptburst# is asserted by the s5335, indicati ng the current pass-thru read is a burst. clock 1: pass-thru status signals indicate what action is requir ed by add-on logic. pass-thru status outputs are valid when ptatn# is active and are sampled by the add-on at the rising edge of clock 2. ptburst# deasserted, the s5335 does not yet recognize a pci burst. ptnum[1:0] 01. indicates the pci ac cess is to pass-thru region 1. ptwr deasserted. the pass-thru access is a read. ptbe[3:0]# 0h. indicate the pass-thru access is 32-bits. the ptadr# input is asserted to read the pass-thru address register. the byte enable, address, and select# inputs are changed during this clock to select the pass-thru data register during clock cycle 3. clock 2: select#, byte enable, and the address inputs remain driven to read the pass-thru data register at offset 2ch. clock 3: wr# asserted at the rising edge of clock 3 writes data 1 into the s5335. ptrdy# asserted at the rising edge of clock 3 completes the current data phase. clock 4: add-on logic drives data 2 on the add-on bus, but ptrdy# deasserted at the rising edge of clock 4 extends the current data phase. clock 5: wr# asserted at the rising edge of clock 5 writes data 2 into the s5335. ptrdy# asserted at the rising edge of clock 5 completes the current data phase. clock 6: add-on logic drives data 3 on the add-on bus, but ptrdy# deasserted at the rising edge of clock 6 extends the current data phase. clock 7: wr# asserted at the rising edge of clock 7 writes data 3 into the s5335. ptrdy# asserted at the rising edge of clock 7 completes the current data phase. on the pci bus, irdy# has been deasserted, causing ptatn# to be deasserted. this is how a pci initiator adds wait states, if it cannot read data quickly enough. clock 8: ptatn# remains deasserted at the rising edge of clock 8. the add-on cannot write data 4 until ptatn# is asserted. add-on logic cont inues to drive data 4 on the add-on bu s. ptatn# is reasserted during the cycle, indicating the pci initiator is done adding wait states. clock 9: wr# asserted at the rising edge of clock 9 writes data 4 into the s5335. ptrdy# asserted at the rising edge of clock 9 completes the current data phase. clock 10: add-on logic drives data 5 on the add-on bus, but pt rdy# deasserted at the rising edge of clock 10 extends the current data phase. clock 11: ptatn# remains deasserted at the rising edge of clock 11. the add-on does not have to write data 5 until ptatn# is asserted. add-on logic continues to drive da ta 5 on the add-on bus. ptatn# is reasserted during the cycle, indicating the pci initiator is done adding wait states. clock 12: ptrdy# asserted at the rising edge of clock 12 complete s the final data phase. any data written into the pass- thru data register is not required and is never passed to the pci interface (as ptrdy# is not asserted at the ris- ing edge of clock 13). clock 13: ptatn# and ptburst# deasserted at the rising edge of clock 13 indicates the pass- thru access is complete. the s5335 can accept new pass-thru accesses from the pci bus at clock 14. s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 156 data sheet add-on pass-thru disconnect operation slow pci targets are prevented from degrading pci bus performance. the pci specification allows only 16 clocks for a target to respond before it must request a retry on single data phase accesses. for burst accesses, the first data phase is allowed 16 clocks to complete, all subsequent data phases are allowed 8 clocks each. this requirement allows other pci initia- tors to use the bus while the target requesting the retry completes the original access. figure 90 shows the conditions that cause the s5335 to request a retry from a pci initiator on the first data phase of a pci read operation. frame# is asserted during the rising edge of pci clock 1. from this point, the s5335 has 16 clock cycles to respond to the initia- tor with trdy# (completing the cycle). frame# could remain asserted, indicating a burst read, but the retry request conditions are identical for a single data phase read and the first data phase of a burst read. bpclk is identical to pciclk, lagging by a propagation delay of a few nanoseconds (see chapter 13). ptatn# is asserted on the add-on interface as soon as frame# is sampled active at a pciclk rising edge. figure 90. target requested retry on the first pci data phase after ptatn# is asserted, ptrdy# must be asserted by the 15th bpclk rising edge to prevent the s5335 from requesting a retry. trdy# is asserted on the pci interface one clock cycle after ptrdy# is asserted on the add-on interface. if a dd-on logic does not return ptrdy# by the 15th bpclk rising edge, the s5335 asserts stop#, requesting a retry from the pci initiator. for pass-thru write operations, the s5335 never dis- connects on the first or second pci data phases of a burst. the first data and second phases are always accepted immediately by the s5335. no further action is required by the pci initiator. the only situation where the s5335 may respond to a pass-thru write with a retry request is after the second data phase of a pass-thru burst write. figure 91 shows the conditions required for the s5335 to request a retry after the second data phase of a burst transfer. this figure applies to both pass-thru burst read and write operations. 18 17 16 15 4 3 2 1 17 16 15 14 3 2 1 pciclk frame# stop# bpclk ptatn# ptrdy # ptrdy # must be asserted by this time to present disconnecting ptrdy # asserted too late so s5335 disconnects (asserts stop#) s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 157 data sheet figure 91. target requested retry after the first data phase of a burst operation the previous data phase is completed with the asser- tion of ptrdy# at the rising edge of bpclk 0. add- on logic must assert ptrd y# by the rising edge of bpclk 8 to prevent the s5335 from asserting stop#, requesting a retry. meeting this condition allows the s5335 to assert trdy# by the rising edge of pciclk 8, completing the data phase with requiring a retry. when the s5335 requests a retry, the pass-thru sta- tus indicators remain valid (allowing the add-on logic to complete the access). ptburst# is the exception to this. ptburst# is deasser ted to indicate that there is currently no burst in progress on the pci bus. the other pass-thru status indicators remain valid until ptatn# is deasserted. figure 92 shows the add-on bus interface signals after the s5335 requests a retry. as long as ptatn# remains asserted, add-on logic should continue to transfer data. for pci read opera- tions, one add-on write operation is required after a retry request. after the add-on write, asserting ptrdy# deasserts ptatn#. for pass-thru write operations, one or two data trans- fers may remain after the s5335 signals a retry. two data transfers are possible because the s5335 has a double buffered pass-thru data register used for writes. a pci burst may have filled both registers before the s5335 requested a retry. ptatn# remains asserted until both are emptied. ptrdy# must be asserted after each read from the pass-thru data reg- ister. if both registers are full, ptatn# is deasserted only after ptrdy# is asserted the second time. the s5335 only accepts further pci accesses after both registers are emptied. 8-bit and 16-bit pass-thru add-on bus interface the s5335 allows a simple interface to devices with 8- bit or 16-bit data buses. each pass-thru region may be defined as 8-, 16-, or 32-bits, depending on the contents of the nv memory boot device loaded into the pci base address configur ation registers during ini- tialization. the pass-thru a dd-on interface internally controls byte lane steering to allow access to the 32- bit pass-thru data register (aptd) from 8-bit or 16- bit add-on buses. 8 7 6 1 9 8 7 2 1 0 pciclk frame# stop# bpclk ptatn# ptrdy# latest assertion of ptrdy# to prevent disconnect ptrdy# asserted too late, results in disconnect pci data transfer s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 158 data sheet figure 92. pass-thru signals after a target requested retry internal byte lane steering may be used whether the mode input defines a 16-bit or 32-bit add-on inter- face. when a 16-bit add-on interface is used, the adr1 input is used in conjunction with the byte enables to steer data into the proper aptd register byte locations. if mode defines a 16-bit interface, only 16-bits of address are driven when ptad r# is asserted. if more than 16-bits of address are required, the pass-thru address register (apta) must be read with select#, rd#, byte enable and address inputs. two consecutive reads are required to latch all of the address information (one with adr1=0, one with adr1=1). regardless of mode, various data widths may be used. for pass-thru writes (add-on aptd reads), add-on logic must read the aptd register one byte or one word at a time (depending on the add-on bus width). the internal data bus is steered to the correct portion of aptd using the be[3:0]# inputs. figure 57 shows the byte lane steering mechanism used by the s5335. the byten symbols indicate data bytes in the pass-thru data register. when a read is performed with a ben# input asserted, the corresponding ptben# out put is deasserted. add- on logic cycles through the byte enables to read the entire aptd register. once all data is read (ptbe[3:0]# are deasserted), ptrdy# is asserted by the add-on, completing the access. for pass-thru reads (add-on aptd writes), the bytes requested by the pci initiator are indicated by the ptbe[3:0]# outputs. add-on logic uses the ptbe[3:0]# signals to determine which bytes must be written (and which bytes have already been written). for example, a pci initiator performs a byte pass-thru read from an 8-bit pass-thru region with pci be2# asserted. on the add-on interface, ptbe2# is asserted, indicating that the pci initiator requires data in this byte. once the add-on writes aptd, byte 2, ptbe2# is deasserted, and the add-on may assert ptrdy#, completing the cycle. figure 58 shows how the external add-on data bus is steered to the pass-thru data register bytes. this mechanism is determined by the pass-thru region bus width defined during initialization (see section 12.3). the byten symbols indicate data bytes in the pass-thru data register. for example, an 8-bit add- on write with be1# asserted results in the data on dq[7:0] being steered into byte1 of the aptd register. bpclk stop# 1 0h fh 2ch 0h ptatn# ptburst# ptnum[1:0] ptwr ptbe[3:0]# select# adr[6:2] be[3:0]# rd# dq[31:0] ptrdy# data s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 159 data sheet table 57. byte lane steering for pass-thru data register read (pci write) byte enables aptd register read byte lane steering 3 2 1 0 dq[31:24] dq[23:16] dq[15:8] dq[7:0] x x x 0 byte3 byte2 byte1 byte0 x x 0 1 byte3 byte2 byte1 byte1 x 0 1 1 byte3 byte2 byte3 byte2 0 1 1 1 byte3 byte3 byte3 byte3 table 58. byte lane steering for pass-thru data register write (pci read) defined pt-bus width aptd register write byte lane steering byte3 byte2 byte1 byte0 32-bit data bus dq[31:24] dq[23:16] dq[15:8] dq[7:0] 16-bit data bus dq[15:8] dq[7:0] dq[15:8] dq[7:0] 8-bit data bus dq[7:0] dq[7:0] dq[7:0] dq[7:0] s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 160 data sheet to write data into the aptd register, the ptben# out- put and the ben# input must both be asserted. the following describes how ap td register writes are controlled: write byte3 if ptbe3# and be3# are asserted write byte2 if ptbe2# and be2# are asserted write byte1 if ptbe1# and be1# are asserted write byte0 if ptbe0# and be0# are asserted after each byte is written into the pass-thru data reg- ister, its corresponding ptbe[3:0]# output is deasserted. this a llows add-on logic to monitor which bytes have been written, and which bytes remain to be written. when all bytes requested by the pci initiator have been written, the ptbe[3:0]# are all be deas- serted, and the add-on asserts ptrdy#. figure 93 shows pass-thru operation for a region defined for an 8-bit add-on bus interface. as the 8-bit device is connected only to dq[7:0], the device must access aptd one byte at a time. the pci initiator has performed a 32-bit write of 08d49a30h to pass-thru region zero. ptbe[3:0]# are all asserted. at clock 1, the add-on begins reading the aptd register (asserting select#, adr[6:2], and rd#). add-on logic asse rts be0#, and byte0 of aptd is driven on dq[7:0]. at the rising edge of clock 2, be0# is sampled by the s5335 and ptbe0# is deasserted. ptbe[3:1]# are still asserted. during clock 2, only be1# is activated, and byte1 of aptd is driven on dq[7:0]. at the rising edge of clock 3, be1# is sampled by the s5335 and ptbe1# is deasserted. ptbe[3:2]# are still asserted. this process continues until all bytes have been read from the aptd register. during clock 5, rd# is deas- serted and ptrdy# is asserted. ptrdy# is sampled by the s5335 at the rising edge of clock 6, and the cur- rent data phase is completed. ptatn# is deasserted and new data can be written from the pci bus. in this example, the byte enables are asserted, sequentially, from be0# to be3#. this is not required, bytes may be accessed in any order. new data is written by the pc i initiator and is available in the aptd register during clock 7. rd# is asserted and the byte enables are cycled again. with each new data from the pci bus, the add-on sequences through the byte enables to access aptd via dq[7:0]. for 16-bit peripheral devices, the byte steering works in the same way. because the add-on data bus is 16- bits wide, only two 16-bit cycles are required to access the entire aptd register. two byte enables can be asserted during each access. in figure 93, rd# is held low and the byte enables are changed each clock. this assumes the add-on can accept data at one byte per cl ock. this is the fastest transfer possible. for slower devices, wait states may be added. as long as the byte enables remain in a given state, the corresponding byte of the aptd register is con- nected to the dq bus (the rd# or wr# pulse may also be lengthened). each access may be extended for slower add-on devices, but extending individual data phases for pass-thru cycl es may result in the s5335 requesting retries by the initiator. figure 93. pass-thru write to an 8-bit add-on device note: 8 bit mode be?s are e, d, b, 7; 16 bit mode be?s are c, 3. 10 11 12 13 9 8 7 6 5 4 3 2 3ch 3ch 2ch fh 0h 1h 3h 7h fh 0h 1h 3h 7h fh 1 bpclk ptatn# ptwr ptbe[3:0]# ptnum[1:0] ptburst# fh bh eh dh 7h fh eh dh bh 7h fh d4h 30h 9ah 08h ddh cch bbh aah addr 0 select# be[3:0]# ptadr# ptrdy# adr[6:2] rd# dq[7:0] s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 161 data sheet configuration the s5335 pass-thru interface utilizes four base address registers (badr1:4 ). each base address register corresponds to a pass-thru region. the con- tents of these registers during initialization determine the characteristics of that particular pass-thru region. each region can be mapped to memory or i/o space. memory mapped devices can, optionally, be mapped below 1 mbyte and can be identified as prefetchable. both memory and i/o regions can be configured as 8-, 16-, or 32-bits wide. the designer has the option to use 1, 2, 3, 4 or none of the pass-thru regions. base address registers are loaded during initialization from the external non-vola- tile boot device. without an external boot device, the default value for the badr r egisters is zero (region disabled). the base address registers are the only registers that define pass-thru operation. s5335 base address register definition some bits in the base address registers have specific functions. the following bits have special functions: badr1:4 bits d31:30 are used only by the s5335. when the host reads the base address registers dur- ing configuration cy cles, they always return the same value as d29. if d29 is zero, d31:30 return zero, indi- cating the region is disabled. if d29 is one, d31:30 return one. this operat ion limits each pass-thru region to a maximum size of 512 mbytes of memory. for i/o mapped regions, the pci specification allows no more than 256 bytes per region. the s5335 allows larger regions to be requested by the add-on, but a pci bios will not allocate the i/o space and will prob- ably disable the region. creating a pass-thru region page 3-40 describes the values that must be pro- grammed into the non-volatile boot device to request various block sizes and char acteristics for pass-thru regions. after reset, the s5335 downloads the con- tents of the boot device lo cations 54h, 58h, 5ch, and 60h into ?masks? for the correspondi ng base address registers. the following are some examples for vari- ous pass-thru region definitions: during the pci bus configuration, the host cpu writes all ones to each base address register, and then reads the contents of the registers back. the mask downloaded from the boot device determines which bits are read back as zeros and which are read back d0 memory or i/o mapping. if this bit is clear, the region should be memory mapped. if this bit is set, the region should be i/o mapped. d2:1 location of a memory region. these bits request that the region be mapped in a particu- lar part of memory. these bit definitions are only used for memory mapped regions. d3 prefetchable. for memory mapped regions, the region can be defined as cacheable. if set, the region is cacheable. if this bit is clear, the region is not. d31:30 pass-thru region bus width. these two bits are used by the s5335 to define the data bus width for a pass-thru region. regardless of the pro- gramming of other bits in the badr register, if d31:30 are zeros, the pass-thru region is dis- abled. d2 d1 location 0 0 anywhere in 32-bit memory space 0 1 below 1 mbyte in memory space (real mode address space) 1 0 anywhere in 64-bit memory space (not valid for the s5335) 11reserved d31 d30 add-on bus width 0 0 region disabled 0 1 8-bits 1 0 16-bits 1 1 32-bits nv memory contents pass-thru region definition 54h = bffff002h pass-thru region 1 is a 4kbyte region, mapped below 1 mbyte in memory space with a 16-bit add-on data bus. this memory region is not cacheable. 58h = 3xxxxxxxh pass-thru region 2 is disabled. (d31:30 = 00.) 60h = ffffff81h pass-thru region 3 is a 32-bit, 128 byte i/o-mapped region. 64h = 00000000h pass-thru region 4 is disabled. s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 162 data sheet as ones. the number of zeros read back indicates the amount of memory or i/o space a particular s5335 pass-thru region is requesting. after the host reads all base address registers in the system (as every pci device implements from one to six), the pci bios allocates memory and i/o space to each base address region. the host then writes the start address of each region back into the base address registers. the start address of a region is always an integer multiple of the region size. for example, a 64 kbyte memory region is always mapped to begin on a 64k boundary in memory. it is important to note that no pci device can xbe abso- lutely located in system me mory or i/o space. all mapping is determined by the system, not the application. accessing a pass-thru region after the system is finished defining all base address regions within a system, each base address register contains a physical address. the application software must now find the location in memory or i/o space of its hardware. pci systems provide bios or operating system function calls for application software to find particular devices on the pci bus based on vendor id and device id values. this allows application software to access the device?s configuration registers. the base address register values in the s5335?s configuration space may then be read and stored for use by the program to access application hardware. the value in the base address registers is the physi- cal address of the first lo cation of that pass-thru region. some processor architectures allow this address to be used directly to access the pci device. for intel architecture systems, the physical address must be changed into a segment/offset combination. for real mode operation in an intel architecture sys- tem (device mapped below 1 mbyte in memory), creating a segment/offset pair is relatively simple. to calculate a physical address, the cpu shifts the seg- ment register 4 bits to the left and adds the offset (resulting in a 20 bit physical address). the value in the base address register must be read and shifted 4 bits to the right. this is the segment value and should be stored in one of the segment registers. an offset of zero (stored in si, di or another offset register) accesses the first location in the pass-thru region. s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 163 data sheet absolute maximum ratings table 59 lists the absolute maximum s5335 device stress ratings. stresses beyond those listed may cause perma- nent damage to the device. these are stress ratings only; op eration of the device at t hese or any other conditions beyond those indicated in the dc characteristics section of this specific ation is no t implied. dc characteristics the following table summarizes the required parameters defined by the pci specification as they apply to the s5335 controller. notes: 1. input leakage applies to all inputs and bi-directional buffers. 2. pci bus signals without pull-up resistors will provide the 3 ma output current. signals which require a pull-up resistor will provide 6 ma out- put current. table 59. absolute maximum ratings parameter min max units storage temperature -55 125 c junction temperature -10 105 c supply voltage (v cc )-0.34v input pin voltage -0.3 6 v esd voltage rating (human body model) 2000 - v esd voltage rating (machine model) 200 - v table 60. recommended operating conditions and dc electrical characteristics symbol parameter min typ m ax units test conditions note s t a operating ambient temperature 0 70 c t j junction temperature -10 85 c v cc supply voltage 3.0 3.3 3.6 v i cc,static supply current (static) - 36 45 ma i cc,dynamic supply current (dynamic) - 50 114 ma v ih input high voltage 2.0 - - v v il input low voltage - - 0.8 v i ih input high leakage current - - +/- 10 a v in = vcc 1 i il input low leakage current - - +/- 10 a v in = gnd 1 v oh output high voltage 2.4 - - v i out = ?1500 a v ol output low voltage - - 0.4 v i out = 1500 a 2 c in input pin capacitance - - 10 pf 3 c clk clk pin capacitance 5 - 12 pf c idsel idsel pin capaticance - - 8 pf s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 164 data sheet 3. the pci specification limits all pci inputs not located on the motherboard to 10 pf (the clock is allowed to be 12 pf). pci bus signals the following table summarizes the pci bus dc parameters de fined by the pci specification as they apply to the s5335 controller. table 61. pci bus signals signal type direction max units notes clk - input - - rst# - input - - inta# open drain output 1.5 ma ad[31:0] t/s bi-directional - ma req# t/s output 1.5 ma gnt# - input - - c/be[3:0]# t/s bi-directional 1.5 ma devsel# s/t/s bi-directional 1.5 ma frame# s/t/s bi-directional 1.5 ma irdy# s/t/s bi-directional 1.5 ma trdy# s/t/s bi-directional 1.5 ma perr# s/t/s bi-directional 1.5 ma par t/s bi-directional 1.5 ma serr# open drain output 1.5 ma stop# s/t/s bi-directional 1.5 ma lock# - input - - idsel - input - - s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 165 data sheet add-on bus signals table 62. add-on bus signals signal type direction max units notes bpclk - output 3 ma irq# - output 1.5 ma sysrst# - output 1.5 ma adr[6:2] - input - - select - input - - adr[6:2] - input - - be[3:0]# - input - - rd# - input - - wr# - input - - dq[31:0] t/s bi-directional 1.5 ma wrfull - output 1.5 ma rdempty - output 1.5 ma rdfifo# - input - - wrfifo# - input - - ptatn# - output 1.5 ma ptburst# - output 1.5 ma ptadr# - input - - ptrdy# - input - - ptwr - output 1.5 ma ptbe[3:0]# - output 1.5 ma ptnum[1:0] - output 1.5 ma eq[7:0] t/s bi-directional 0.5 ma ea[8:0] t/s output 0.5 ma ea[15:9] - output 0.5 ma mode - input - - test - output 1.5 ma flt# - input - - s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 166 data sheet ac characteristics pci bus timing note: 1. minimum times are for unloaded outputs, maximum times are for 10 pf equivalent loads. figure 94. pci clock timing erd#/scl - output 0.5 ma ewr#/sda t/s bi-directional 0.5 ma table 62. add-on bus signals signal type direction max units notes table 63. pci bus timing functional operation range (v cc = 3.3v 5%, 0c to 70c, 10 pf load on outputs) symbol parameter min max units notes tcl cycle time 30 - ns t 1 high time 11 - ns t 2 low time 11 - ns t 3 rise time (0.2v cc to 0.6v cc )14ns t 4 fall time (0.6v cc to 0.2v cc )14ns t 5 output valid delay (bussed signals) output valid delay (point-to-point signals) 2 2 11 12 ns note 1 t 6 float to active delay 2 - ns t 7 active to float delay - 28 ns t 8 rising edge setup (bussed signals) rising edge setup (gnt#) rising edge setup (req#) 7 10 12 - - - ns t 9 hold from pci clock rising edge 0 - ns t 10 pciclk to bpclk delay 2 7 ns t 1 v ih2 t 2 t 3 t 4 0.6vcc 0.6vcc 0.2vcc tcl s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 167 data sheet figure 95. pci output timing figure 96. pci input timing pci clk output delay tri-state output t 5 t 6 1.5 1.5 1.5 1.5 t 7 pci clk t 8 t 9 input inputs valid s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 168 data sheet add-on bus timings figure 97. add-on clock timing figure 98. pass-thru clock relationship to pci clock 0.6vcc t 1 0.2vcc t 2 t 3 t 4 0.6vcc 0.2vcc tcl v ih 2 pci clk bpclk t 10 s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 169 data sheet synchronous rdfifo# timing notes: 1. valid applies after first acce ss. first access is async with following as sync accesses. 2. state change of rdempty shown below is reference only. figure 99. synchronous rdfifo# timing table 64. synchronous rdfifo# timing functional operation range (v cc = 3.3v 5%, 0c to 70c, 50 pf load on outputs) symbol parameter min max units notes t 144 rdfifo# setup to bpclk rising edge 15 - ns t 145 rdfifo# low time 8 - ns t 146 rdfifo# low to dq[31:0] driven - 13 ns t 148 rdfifo# high to dq[31:0] float - 8 ns t 149 dq[31:0] valid from bpclk rising edge - 15 ns t 165 pci to add-on fifo rdempty valid from bpclk rising edge - 15 ns t 166 pci to add-on fifo frf valid from bpclk rising edge - 80 ns rdfifo# dq[31:0] rdempty frf 8ns old valid new valid bpclk 6ns 14ns t 144 10ns t 149 t 146 t 165 t 148 t 166 s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 170 data sheet synchronous wrfifo# timing note: 1. state change of wrfull shown below is reference on ly. actual change would indicate no data 3 written. figure 100. synchronous wrfifo# timing table 65. synchronous wrfifo timing functional operation range (v cc = 3.3v 5%, 0c to 70c, 50 pf load on outputs) symbol parameter min max units notes t 150 wrfifo# setup to bpc lk rising edge 15 - ns t 150a wrfifo# hold time to bpclk rising edge 2 - ns t 151 dq[31:0] setup to bpclk rising edge 15 - ns t 151a dq[31:0] hold from bpclk rising edge 0 - ns t 167 add-on to pci wrfull valid from bpclk rising edge - 15 ns 1 t 168 add-on to pci fifo fwe vali d from bpclk rising edge - 26 ns wrfifo# dq[31:0] wrfull fwe 6ns old valid new valid bpclk 1 2 3 t 150 t 151 t 150a t 167 t 168 t 151a s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 171 data sheet asynchronous rd# register access timing note: for non-burst fifo read/write operations figure 101. asynchronous rd# fifo timing table 66. asynchronous rd# register access timing functional operation range (v cc =3.3v 5%, 0c to 70c, 50 pf load on outputs) symbol parameter m in max units notes t 110 select# setup to rd# rising edge 10 - ns t 110a select# hold from rd# rising edge 0 - ns t 114 adr[6:2] setup to rd# rising edge 10 - ns t 114a adr[6:2] hold from rd# rising edge 0 - ns t 118 be[3:0]# setup to rd# rising edge 10 - ns t 118a be[3:0]# hold from rd# rising edge 0 - ns t 129 rd# high time 15 - ns t 130 rd# low time 15 - ns t 133 dq[31:0] valid from rd# falling edge 13 - ns t 133a dq[31:0] hold from rd# rising edge 2 - ns t 152 rdempty status valid from rd# rising edge - 15 ns t 153 frf status valid from rd# rising edge - 75 ns select# t 110 adr[6:2] be[3:0]# dq[31:0] rd# t 114 t 118 t 133 t 130 t 133a 5ns t 152 t 153 t 129 rdempty frf s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 172 data sheet asynchronous wr# register access timing note: for non-burst fifo read/write operations figure 102. asynchronous wr# fifo timing table 67. asynchronous wr# register access timing functional operation range (v cc = 3.3v 5%, 0c to 70c, 50 pf load on outputs) symbol parameter min max units notes t 111 select# setup to wr# rising edge 8 - ns t 111a select# hold from wr# rising edge 0 - ns t 115 adr[6:2] setup to wr# rising edge 8 - ns t 115a adr[6:2] hold from wr# rising edge 0 - ns t 119 be[3:0]# setup to wr# rising edge 8 - ns t 119a be[3:0]# hold from wr# rising edge 0 - ns t 132 wr# low time 4 - ns t 134 dq[31:0] setup to wr# rising edge 5 - ns t 134a dq[31:0] hold from wr# rising edge 3 - ns t 154 wrfull status valid from wr# rising edge - 27 ns t 155 fwe status valid from wr# rising edge - 40 ns select# t 111 adr[6:2] be[3:0]# dq[31:0] wr# wrfull 13ns fwe t 115 t 119 t 134 t 134a t 132 t 154 t 155 s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 173 data sheet synchronous rd# fifo timing notes: 1. rd# and select# must both be asserted to drive dq[31:0] - delay is from the last one asserted. 2. when increasing setup times, adr[6:2], be[3:0]#, select#, and rd# timing relations remain relative to each other as shown. figure 103. synchronous rd# fifo timing table 68. synchronous rd# fifo timing functional operation range (v cc = 3.3v 5%, 0c to 70c, 50 pf load on outputs) symbol parameter min max units notes t 112 select# setup to bpclk rising edge 15 - ns t 112a select# hold from bpclk rising edge 0 - ns t 116 adr[6:2] setup to bpclk rising edge 22 - ns t 116a adr[6:2] hold from bpclk rising edge 0 - ns t 120 be[3:0]# setup to bpclk rising edge 17 - ns t 120a be[3:0]# hold from bpclk rising edge 0 - ns t 125 rd# low to dq[31:0] driven - 13 ns t 128 rd# high to dq[31:0] float - 8 ns t 156 rdempty status valid to bpclk rising edge - 15 ns t 157 frf status valid to bpclk rising edge - 74 ns t 124 rd# setup to bpclk rising edge 15 - ns t 124a rd# hold from bpclk rising edge 0 - ns t 127 dq[31:0] valid from bpclk rising edge - 15 ns bpclk select# adr[6:2] be[3:0]# dq[31:0] rd# rdempty frf 5ns t 112 t 112a t 116 t 116a t 120 t 120a t 125 t 124 t 124a t 156 t 128 t 157 s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 174 data sheet synchronous multiple rd# fifo timing figure 104. synchronous rd# fifo timing bpclk select# adr[6:2] be[3:0] dq[31:0] rd# rdempty frf 4 5 6 7 5ns 2ns 5ns 3 2 11ns t 124 8 t 125 t 120 t 116 t 112 t 157 t 112a t 116a t 120a t 124a t 156 s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 175 data sheet synchronous wr# fifo timing figure 105. synchronous wr# fifo timing table 69. synchronous wr# fifo timing functional operation range (v cc = 3.3v 5%, 0c to 70c, 50 pf load on outputs) symbol parameter m in max units notes t113 select# setup to bpclk rising edge 15 - ns t113a select# hold from bpclk rising edge 0 - ns t117 adr[6:2] setup to bpclk rising edge 15 - ns t117a adr[6:2] hold from bpclk rising edge 0 - ns t121 be[3:0]# setup to bpclk rising edge 15 - ns t121a be[3:0]# hold from bpclk rising edge 0 - ns t123 dq[31:0] setup to bpclk rising edge 15 - ns t123a dq[31:0] hold from bpclk rising edge 0 - ns t122 wr# setup to bpclk rising edge 15 - ns t122a wr# hold from bpclk rising edge 0 - ns t159 wrfull status valid to bpclk rising edge - 15 ns t160 fwe status valid to bpclk rising edge - 15 ns bpclk select# t 113 adr[6:2] be[3:0]# dq[31:0] wr# t 117 t 121 t 123 t 122 t 123a wrfull 3ns t 159 fwe 4ns t 160 s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 176 data sheet synchronous multiple wr# fifo timing figure 106. synchronous multiple wr# fifo timing b p c l k s e l e c t # a d r [ 6 : 2 ] b e [ 3 : 0 ] # d q [ 3 1 : 0 ] w r # t 1 2 3 a 3 4 5 6 7 w r f u l l 3 n s 4 n s t 1 2 3 a t 1 6 0 t 1 1 3 t 1 1 7 t 1 2 1 t 1 2 3 t 1 2 3 t 1 2 2 2 1 8 t 1 5 9 s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 177 data sheet target s5335 pass-thru interface timing note: 1. this timing also applies to the use of be[3:0]# to control dq[31:0] drive. table 70. pass-thru interface timing functional operation range (v cc = 3.3v 5%, 0c to 70c, 50 pf load on outputs) symbol parameter min max units notes t 10a select# setup to bpclk rising edge 15 - ns t 11a select# hold from bpclk rising edge 0 - ns t 12 adr[6:2], be[3:0]# to valid dq [31:0] - 16 ns t 13 adr[6:2], be[3:0]# setup to bpclk rising edge 15 - ns t 14 adr[6:2], be[3:0]# hold from bpclk rising edge 0 - ns t 17 rd# low to dq{31:0] driven - 13 ns 1 t 24 pass-thru status valid from bpclk rising edge - 6 ns t 25 pass-thru status hold from bpclk rising edge 0 - ns t 26 ptrdy# setup to bpclk rising edge 15 - ns t 27 ptrdy# hold from bpclk rising edge 0 - ns t 29 rd#, wr# setup to bpclk rising edge 15 - ns t 30 rd#, wr# hold from bpclk rising edge 2 - ns t 31 dq[31:0] setup to bpclk rising edge 15 - ns t 32 dq[31:0] hold from bpclk rising edge 0 - ns t 33 dq[31:0] valid from bpclk rising edge - 15 ns t 34 dq[31:0] float from rd# rising edge - 12 ns s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 178 data sheet figure 107. pass-thru data register read timing figure 108. pass-thru data register write timing t 14 t 13 t 29 t 12 t 30 t 33 t 17 t 34 t 11a t 27 t 26 bpclk dq[31:0] rd# select# ptrdy# adr[6:2] be[3:0]# valid 2 valid data out 2 valid 1 valid data out 1 t 14 t 13 t 32 t 31 t 29 t 30 t 11a t 27 t 26 t 10a bpclk dq[31:0] wr# select# ptrdy# adr[6:2] be[3:0]# valid 2 valid data in 2 valid 1 valid data in 1 s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 179 data sheet figure 109. pass-thru status indicator timing target byte-wide nv me mory interface timing notes: 1. t represents the clock period for the pci bus clock (30ns @ 33 mhz). 2. the write cycle time is controlled by both the pci bus clock and software operations to initiate the write operation of nv me mory. this param- eter is the result of several software operations to the bus master control/status register (mcsr). bpclk ptatn# ptwr ptburst# ptnum[1:0] ptbe[3:0]# valid valid t 24 t 25 table 71. target byte-wide memory interface timing functional operation range (v cc =3.3v 5%, 0c to 70c , 50 pf load on outputs) symbol parameter m in max units notes t 35 erd# cycle time 8t - ns note 1 t 36 erd# low time 6t - ns note 1 t 37 erd# high time 2t - ns note 1 t 38 ea[15:0] setup to erd# or ewr# low t - ns note 1 t 39 ea[15:0] hold from erd# or ewr# high t - ns note 1 t 40 eq[7:0] setup to erd# rising edge 10 - ns note 1 t 41 eq[7:0] hold from erd# rising edge 2 - ns note 1 t 43 ewr# low time 6t - ns note 1 t 44 ewr# high time 2t - ns note 1 t 45 eq[7:0] setup to ewr# low -10 0 - ns note 1 t 46 eq[7:0] hold from ewr# high t - ns note 1 s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 180 data sheet figure 110. nv memory read timing figure 111. nv memory write timing data valid eq[7:0] (input) ea[15:0] (output) erd# (output) address valid t 35 t 36 t 37 t 39 t 38 t 41 t 40 data valid eq[7:0] (output) ea[15:0] (output) ewr# (output) address valid t 42 t 43 t 44 t 39 t 46 t 45 t 38 s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 181 data sheet target timing notes: 1. this timing applies to interrupts gen erated and cleared from the pci interface. figure 112. irq# interrupt output timing figure 113. mailbox 4, by te 3 direct input timing table 72. target interrupt timing functional operation range (v cc =3.3v 5%, 0c to 70c , 50 pf load on outputs) symbol parameter min max units notes t 49 irq# low from bpclk rising edge - 15 ns note 1 t 50 irq# high from bpclk rising edge - 15 ns note 1 table 73. mailbox timing functional operation range (v cc = 3.3v 5%, 0c to 70c, 50 pf load on outputs) symbol parameter min max units notes t 51 embclk low time 12 - ns t 52 emblk high time 12 - ns t 53 emb[7:0] setup to embclk rising edge 5 - ns t 54 emb[7:0] hold from embclk rising edge 2 - ns bpclk irq# t 50 t 49 embclk emb[7:0] t 51 t 52 t 54 t 53 valid s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 182 data sheet figure 114. s5335 pinout and pin assignment - 176 lqfp (low profile quad flat package) s5335 (176 lqfp) 1 eq0 ad23 ad22 ad21 dq31 ad20 ad19 ad18 eq1 gnd vcc ad17 dq30 ad16 c/be2# frame# eq2 irdy# trdy# eq3 stop# lock# perr# dq29 serr# par c/be1# eq4/fwc# gnd vcc ad15 eq5/frc# ad14 ad13 ad12 dq28 ad11 ad10 ad9 ptbe3# ptbe2# ptbe1# dq20 ptbe0# ptrdy# ptatn# ea9 ptburst# vcc gnd ea8 ptwr ptadr# rdempty dq21 rdfifo# wrfull wrfifo# ea7 dq0 dq1 dq2 ea6 dq3 dq4 dq5 dq22 dq6 ea5 dq7 beo# dq8 dq23 dq9 dq10 dq11 ea4 dq13 dq12 dq14 dq24 dq15 select# wr# ea3 rd# vcc gnd ea2 adr2 adr3 adr4 dq25 adr5 be1# be2# ea1 be3#/adr1 mode inta# ea0 ad0 ad1 ad2 dq26 ad3 eq7/amwen ad4 ad5 ad6 dq27 ad7 c/be0# ad8 eq6/amren ea10 ptnum1 ptnum0 irq# dq19 sysrst# ewr#/sda erd#/scl ea11 adr6 dq18 snv ea12 rsvd rst# bpclk ea13 clk gnt# req# dq17 ad31 ad30 ad29 ea14/fwe ad28 ea15/frf ad27 ad26 ad25 dq16 ad24 c/be3# idsel 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 128 127 126 125 124 123 122 121 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 88 87 86 85 165 166 167 168 169 170 171 172 173 174 175 176 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 vcc gnd 84 83 82 81 161 162 163 132 131 130 129 41 42 43 44 164 gnd vcc gnd vcc gnd vcc vcc gnd vcc gnd vcc gnd vcc gnd vcc gnd gnd gnd vcc gnd vcc gnd vcc vcc rev. 1.5 (8/25/04) devsel# s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 183 data sheet s5335 ? 176 lqfp package ma rking drawing (top view) figure 115. s5335 ? 176 lqfp package marking drawing (top view) notes (unless otherwise specified): 2 dot represents pin 1 (a01) designator es (engineering sample) designator . when present, this signifies pre-production grade material. pre-production grade material is not guaranteed to meet the specific ations in this document. S5335QFAAB xxyy zzzzzzm jjjjjjjj taiwan m es legend (in row order - including symbols): row #1: amcc logo row #2: amcc device part number row #3: mask protection symbol xx: assembly year code yy: assembly week code row #4: zzzzzz: amcc 6 digit lot code m: mask set revision code row #5: jjjjjjjj: up to 8 digit subcontractor lot code row #6: esd symbol taiwan: assembly location row #7: engineering sample (es) designator (only on pre-production devices) m 2 1 1 pci matchmaker s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 184 data sheet figure 116. package physical dimensions - 176 lqfp package material note: standard package: pin composition - 85sn/15pb. green/rohs compliant package: pin composition - 98sn/2.0cu air flow theta ja theta jc 0 m/sec 42.9 c/w 11.4 c/w 1 m/sec 41.3 c/w 2 m/sec 39.2 c/w thermal management ( t a = 70 c) s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 185 data sheet table 74. s5335 numerical pin assignment - 176 lqfp pin# signal type pin# signal type pin# signal type 1 ad27 t/s 32 par t/s 63 dq28 t/s 2 gnd v 33 c/be1# t/s 64 eq6/amren t/s 3 ad26 t/s 34 gnd v 65 vcc v 4 ad25 t/s 35 ad15 t/s 66 dq27 t/s 5 ad24 t/s 36 ad14 t/s 67 eq7/amwen t/s 6 vcc v 37 ad13 t/s 68 dq26 t/s 7 c/be3# t/s 38 vcc v 69 ea0 t/s 8 idsel in 39 ad12 t/s 70 mode in 9 ad23 t/s 40 ad11 t/s 71 be3#/adr1 in 10 gnd v 41 ad10 t/s 72 gnd v 11 ad22 t/s 42 gnd v 73 ea1 t/s 12 ad21 t/s 43 ad9 t/s 74 be2# in 13 ad20 t/s 44 ad8 t/s 75 be1# in 14 vcc v 45 c/be0# t/s 76 adr5 in 15 ad19 t/s 46 vcc v 77 dq25 t/s 16 ad18 t/s 47 ad7 t/s 78 adr4 in 17 ad17 t/s 48 ad6 t/s 79 adr3 in 18 gnd v 49 ad5 t/s 80 adr2 in 19 ad16 t/s 50 gnd v 81 ea2 t/s 20 c/be2# t/s 51 ad4 t/s 82 vcc v 21 frame# t/s 52 ad3 t/s 83 rd# in 22 vcc v 53 ad2 t/s 84 ea3 t/s 23 irdy# t/s 54 vcc v 85 wr# in 24 trdy# t/s 55 ad1 t/s 86 select# in 25 devsel# t/s 56 ad0 t/s 87 dq15 t/s 26 gnd v 57 dq31 t/s 88 dq24 t/s 27 stop# t/s 58 dq30 t/s 89 dq14 t/s 28 lock# in 59 dq29 t/s 90 gnd v 29 perr# t/s 60 gnd v 91 dq13 t/s 30 vcc v 61 eq4/fwc# t/s 92 dq12 t/s 31 serr# o/d 62 eq5/frc# t/s 93 ea4 t/s s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 186 data sheet table 74. s5335 numerical pin as signment - 176 lqfp (continued) pin# signal type pin# signal type pin# signal type 94 dq11 t/s 125 ea8 t/s 156 ea14/fwe out 95 vcc v 126 ptburst# out 157 ea15/frf out 96 dq10 t/s 127 ea9 t/s 158 gnd v 97 dq9 t/s 128 vcc v 159 dq16 t/s 98 dq23 t/s 129 ptatn# out 160 eq0 t/s 99 dq8 t/s 130 ptrdy in 161 vcc v 100 gnd v 131 ptbe0# out 162 eq1 t/s 101 be0# in 132 dq20 t/s 163 eq2 t/s 102 dq7 t/s 133 ptbe1# out 164 eq3 t/s 103 ea5 t/s 134 ptbe2# out 165 inta# out 104 dq6 t/s 135 gnd v 166 rsvd in 105 dq22 t/s 136 ptbe3# out 167 rst# in 106 vcc v 137 ea10 out 168 clk in 107 dq5 t/s 138 ptnum1 out 169 gnt# in 108 dq4 t/s 139 ptnum0 out 170 req# out 109 dq3 t/s 140 irq# out 171 gnd v 110 ea6 t/s 141 dq19 t/s 172 ad31 t/s 111 gnd v 142 vcc v 173 ad30 t/s 112 dq2 t/s 143 sysrst# out 174 vcc v 113 dq1 t/s 144 ewr#/sda t/s 175 ad29 t/s 114 dq0 t/s 145 gnd v 176 ad28 t/s 115 ea7 t/s 146 erd#/scl out 116 wrfifo# in 147 ea11 out 117 vcc v 148 vcc v 118 wrfull out 149 adr6 in 119 rdfifo# in 150 dq18 t/s 120 dq21 t/s 151 snv in 121 rdempty out 152 ea12 out 122 ptadr# in 153 ea13 out 123 gnd v 154 bpclk out 124 ptwr# out 155 dq17 t/s s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 187 data sheet document revision history revision date description 5.01 11/30/05 ? page 23, removed figure 6 ? page 183, added figure 115, s5335 ? 176 lqfp package marking drawing (top view) ? page 184, added note to below figure 116 5.00 01/31/05 ? page 107, updated second paragraph of add-on bus interface ? page 111, updated first paragraph of fifo bus interface ? page 163, table 60, updated icc ? page 171, table 66, added foot note ? page 172, table 67, updated t134a and added foot note ? page 173, table 68, updated t116 and t120 ? page 177, table 70, updated t30 4.00 12/16/04 ? page 200, added development kit ordering information 3.10 8/26/04 ? page 3, updated feature list. ? page 29, table 10 updated scl signal type ? page 29, table 11 updated ea[15:0] signal type ? page 176, table 61 updated devsel current ? page 177, table 62 corrected bpclk signal name ? page 178, table 63 updated output load and t10 ? page 181, table 64 updated t144, t146, t148, t149, and t165 ? page 182, table 65 updated t150, t150a, t151, and t167 ? page 183, table 66 updated t110a, t114, t118, t133, t133a, and t152 ? page 184, table 67 updated t111, t119, t134, and t134a ? page 185, table 68 updated t112, t112a, t116, t116a, 120, t120a, t125, t156, t124, t124a, and t127 ? page 187, table 69 updated t113, t117, t123, t123a, t122, t159, and t160 ? page 189, table 70 updated t10a, t11a, t13, t14, t24, t26, t27, t29, t30, t31, and t32 ? page 195, figure 115, added signal name to pin 25 ? page 196, updated signal type for pin 130, 137, 146, 147,149, 152, 153, 156, 157, and 166 3.00 5/29/04 ? (page 175, table 59) updated t j ? (page 175, table 60) added t j ? (page 175, table 60) updated iil and iih ? page 198 updated ordering part number s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 188 data sheet 2.00 4/27/04 ? page 3, updated package information. ? (page 175, table 59) deleted power dissipation, added t j and esd rating ? (page 175, table 59) added t a , i cc , updated vih, vil, voh, vol, iil, iih ? (page 178, table 63) updated t7 ? (page 181, table 64) updated t144 and t148 ? (page 181 figure 100) updated rdfifo# timing diagram ? (page 182, table 65) updated t151 and t151a ? (page 182, figure 101) updated timing diagram ? (page 183, table 66) updated t110a, t114a, t129 ? (page 184, table 67) deleted t131 ? (page 184, figure 103) updated t134a labeling ? (page 185, table 68) updated t112, t116, t120, t125, t124 ? (page 185, figure 104) updated select# timing diagram ? (page 189, table 70) deleted t28 ? (page 191, table 71) deleted t42 ? (page 195, figure 115) replace nandout (#148) with vcc ? (page 196, figure 116) updated package spec, added thermal management data ? page 197 updated pin 148 ? page 199 added document revision history revision date description s5335 ? pci bus controller, 3.3v revision 5.01 ? november 30, 2005 amcc confidential and proprietary ds1657 189 data sheet ordering information applied micro circuits corporation 6290 sequence dr., san diego, ca 92121 phone: (858) 450-9333 ? (800) 755-2622 ? fax: (858) 450-9885 http://www.amcc.com amcc reserves the right to make changes to its products, its datasheets, or related docum entation, without notice and war- rants its products solely pursuant to its terms and conditions of sale, only to substantially co mply with the la test available datasheet. please consult amcc?s term and condi tions of sale for its warranties and ot her terms, conditions and limitations. amcc may discontinue any semiconductor product or service wit hout notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the inform ation is current. amcc does not assume any lia - bility arising out of the application or use of any product or circuit described herein, neither does it convey any license und er its patent rights nor the rights of others. amcc reserves the ri ght to ship devices of higher grade in place of those of lower grade. amcc semiconductor products are not designed, intended, authorized, or warranted to be suitable for use in life-support applications, devices or systems or other critical applications. amcc is a registered trademark of appli ed micro circuits corporati on. copyright ? 2005 applied micro circuits corporation. dev ice s5335 qf = 176 pin lqfp blank = standard aab = lead free package options package p/n s5335dk description the kit includes: development kit manual evaluation board schematic, pcb, cpld, bom, nvram tool, application software device ordering part num ber developm ent kit ordering part num ber dev ice sxxxx package/type xx option xxx |
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